Alternatives and similar repositories for ara

Users that are interested in ara are comparing it to the libraries listed below

• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆295Updated last year
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆532Updated last month
• RV-BOSC / OpenNoC
  ☆195Updated 3 months ago
• sld-columbia / esp
  Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
  ☆384Updated 2 months ago
• ucb-bar / berkeley-hardfloat
  ☆347Updated 3 weeks ago
• tukl-msd / DRAMSys
  DRAMSys a SystemC TLM-2.0 based DRAM simulator.
  ☆306Updated last week
• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆440Updated 4 months ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆660Updated last week
• davidepatti / noxim
  Network on Chip Simulator
  ☆287Updated 2 months ago
• mariusmm / RISC-V-TLM
  RISC-V SystemC-TLM simulator
  ☆324Updated 9 months ago
• pulp-platform / pulp
  This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…
  ☆513Updated 10 months ago
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆599Updated last week
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆183Updated 10 months ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆228Updated this week
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆211Updated last month
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆266Updated last week
• RoaLogic / RV12
  RISC-V CPU Core
  ☆387Updated 3 months ago
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆611Updated this week
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆297Updated this week
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆218Updated 5 years ago
• chipsalliance / Cores-VeeR-EH2
  ☆244Updated 2 years ago
• schoeberl / chisel-lab
  Lab exercises for Chisel in the digital electronics 2 course at DTU
  ☆210Updated 4 months ago
• umd-memsys / DRAMsim3
  DRAMsim3: a Cycle-accurate, Thermal-Capable DRAM Simulator
  ☆411Updated last year
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆273Updated last week
• XUANTIE-RV / riscv-matrix-extension-spec
  A matrix extension proposal for AI applications under RISC-V architecture
  ☆152Updated 7 months ago
• riscv-software-src / riscv-perf-model
  Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model
  ☆189Updated 2 weeks ago
• sparcians / map
  Modeling Architectural Platform
  ☆206Updated this week
• Xilinx / libsystemctlm-soc
  SystemC/TLM-2.0 Co-simulation framework
  ☆256Updated 4 months ago
• NVlabs / matchlib
  SystemC/C++ library of commonly-used hardware functions and components for HLS.
  ☆282Updated 2 weeks ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆175Updated last month