The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core
☆522May 6, 2026Updated 2 weeks ago
Alternatives and similar repositories for ara
Users that are interested in ara are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Vector processor for RISC-V vector ISA☆139Oct 19, 2020Updated 5 years ago
- RISC-V Zve32x Vector Coprocessor☆217Jan 22, 2026Updated 3 months ago
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,939May 13, 2026Updated last week
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆153May 12, 2026Updated last week
- Chisel RISC-V Vector 1.0 Implementation☆146Apr 23, 2026Updated 3 weeks ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- GPGPU processor supporting RISCV-V extension, developed with Chisel HDL☆905May 10, 2026Updated last week
- ☆265Dec 22, 2022Updated 3 years ago
- A matrix extension proposal for AI applications under RISC-V architecture☆181Apr 1, 2026Updated last month
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,251Apr 29, 2026Updated 3 weeks ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆603May 7, 2026Updated last week
- Working draft of the proposed RISC-V V vector extension☆1,079Mar 17, 2024Updated 2 years ago
- Ocelot: The Berkeley Out-of-Order Machine With V-EXT support☆247Jan 14, 2026Updated 4 months ago
- ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!☆229Nov 22, 2023Updated 2 years ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆212Updated this week
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- The multi-core cluster of a PULP system.☆114Updated this week
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆334Updated this week
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,231Apr 17, 2026Updated last month
- Common SystemVerilog components☆747May 7, 2026Updated last week
- ☆316May 13, 2026Updated last week
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,581Updated this week
- Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit☆39Dec 23, 2021Updated 4 years ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆86Apr 1, 2026Updated last month
- ☆200Dec 14, 2023Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Berkeley's Spatial Array Generator☆1,306Mar 29, 2026Updated last month
- RiVEC Bencmark Suite☆132Nov 27, 2024Updated last year
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Jan 19, 2021Updated 5 years ago
- VeeR EH1 core☆942May 29, 2023Updated 2 years ago
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆166Jan 25, 2024Updated 2 years ago
- Instruction Set Generator initially contributed by Futurewei☆309Oct 17, 2023Updated 2 years ago
- ☆374Apr 25, 2026Updated 3 weeks ago
- ☆379Sep 12, 2025Updated 8 months ago
- Tile based architecture designed for computing efficiency, scalability and generality☆290Apr 30, 2026Updated 2 weeks ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- A Fast, Low-Overhead On-chip Network☆294May 12, 2026Updated last week
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,161Mar 11, 2026Updated 2 months ago
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,875May 7, 2026Updated last week
- 32-bit Superscalar RISC-V CPU☆1,247Sep 18, 2021Updated 4 years ago
- VeeR EL2 Core☆338May 13, 2026Updated last week
- A scalable 256/1024-RISC-V-core system with low-latency access into shared L1 memory.☆319Updated this week
- FuseSoC-based SoC for VeeR EH1 and EL2☆342Dec 11, 2024Updated last year