Alternatives and similar repositories for ara

Users that are interested in ara are comparing it to the libraries listed below

• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆512Updated 5 months ago
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆290Updated last year
• ucb-bar / berkeley-hardfloat
  ☆334Updated 10 months ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆637Updated last week
• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆436Updated 2 months ago
• RV-BOSC / OpenNoC
  ☆176Updated last month
• tukl-msd / DRAMSys
  DRAMSys a SystemC TLM-2.0 based DRAM simulator.
  ☆294Updated 2 months ago
• sld-columbia / esp
  Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
  ☆381Updated 3 weeks ago
• davidepatti / noxim
  Network on Chip Simulator
  ☆283Updated 2 weeks ago
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆593Updated last week
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆207Updated 2 months ago
• pulp-platform / pulp
  This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…
  ☆505Updated 8 months ago
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆569Updated 3 weeks ago
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆180Updated 7 months ago
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆292Updated last week
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆263Updated last month
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆216Updated last week
• mariusmm / RISC-V-TLM
  RISC-V SystemC-TLM simulator
  ☆314Updated 7 months ago
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆218Updated 4 years ago
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆718Updated 3 months ago
• RoaLogic / RV12
  RISC-V CPU Core
  ☆359Updated last month
• sparcians / map
  Modeling Architectural Platform
  ☆196Updated this week
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆195Updated last year
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆265Updated 3 months ago
• ic-lab-duth / RISC-V-Vector
  Vector processor for RISC-V vector ISA
  ☆122Updated 4 years ago
• Xilinx / libsystemctlm-soc
  SystemC/TLM-2.0 Co-simulation framework
  ☆252Updated 2 months ago
• schoeberl / chisel-lab
  Lab exercises for Chisel in the digital electronics 2 course at DTU
  ☆205Updated last month
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆162Updated last month
• chipsalliance / Cores-VeeR-EH2
  ☆240Updated 2 years ago
• ucb-bar / riscv-mini
  Simple RISC-V 3-stage Pipeline in Chisel
  ☆586Updated 11 months ago