pulp-platform / araLinks
The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core
☆453Updated 3 weeks ago
Alternatives and similar repositories for ara
Users that are interested in ara are comparing it to the libraries listed below
Sorting:
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆525Updated 2 weeks ago
- Instruction Set Generator initially contributed by Futurewei☆292Updated last year
- Common SystemVerilog components☆649Updated this week
- This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…☆438Updated 3 months ago
- Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy☆381Updated last month
- ☆336Updated 11 months ago
- ☆184Updated 2 months ago
- BaseJump STL: A Standard Template Library for SystemVerilog☆598Updated last week
- This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…☆509Updated 8 months ago
- A Chisel RTL generator for network-on-chip interconnects☆207Updated this week
- DRAMSys a SystemC TLM-2.0 based DRAM simulator.☆299Updated 3 months ago
- Functional verification project for the CORE-V family of RISC-V cores.☆583Updated last week
- VeeR EL2 Core☆294Updated last week
- RISC-V SystemC-TLM simulator☆317Updated 8 months ago
- Network on Chip Simulator☆287Updated last month
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆217Updated 5 years ago
- RISC-V Debug Support for our PULP RISC-V Cores☆266Updated 4 months ago
- A Fast, Low-Overhead On-chip Network☆221Updated 3 weeks ago
- SystemC/TLM-2.0 Co-simulation framework☆254Updated 3 months ago
- Chisel examples and code snippets☆257Updated 3 years ago
- RISC-V Torture Test☆197Updated last year
- A Linux-capable RISC-V multicore for and by the world☆721Updated this week
- Modeling Architectural Platform☆200Updated 2 weeks ago
- A matrix extension proposal for AI applications under RISC-V architecture☆151Updated 6 months ago
- RISC-V CPU Core☆369Updated 2 months ago
- Simple RISC-V 3-stage Pipeline in Chisel☆588Updated last year
- The OpenPiton Platform☆727Updated last month
- ☆242Updated 2 years ago
- Lab exercises for Chisel in the digital electronics 2 course at DTU☆206Updated 2 months ago
- Verilog Configurable Cache☆181Updated 8 months ago