Alternatives and similar repositories for ara

Users that are interested in ara are comparing it to the libraries listed below

• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆501Updated 4 months ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆627Updated this week
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆288Updated last year
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆556Updated 2 weeks ago
• ucb-bar / berkeley-hardfloat
  ☆328Updated 9 months ago
• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆426Updated last month
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆581Updated last week
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆286Updated 2 weeks ago
• mariusmm / RISC-V-TLM
  RISC-V SystemC-TLM simulator
  ☆311Updated 6 months ago
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆258Updated 2 months ago
• RV-BOSC / OpenNoC
  ☆162Updated last month
• sld-columbia / esp
  Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
  ☆375Updated 2 weeks ago
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆261Updated this week
• pulp-platform / pulp
  This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…
  ☆497Updated 6 months ago
• RoaLogic / RV12
  RISC-V CPU Core
  ☆337Updated last week
• Xilinx / libsystemctlm-soc
  SystemC/TLM-2.0 Co-simulation framework
  ☆247Updated last month
• chipsalliance / Cores-VeeR-EH2
  ☆238Updated 2 years ago
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆214Updated 4 years ago
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,308Updated this week
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆708Updated last month
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆320Updated 6 months ago
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆199Updated last month
• tukl-msd / DRAMSys
  DRAMSys a SystemC TLM-2.0 based DRAM simulator.
  ☆280Updated last month
• schoeberl / chisel-examples
  Chisel examples and code snippets
  ☆254Updated 2 years ago
• schoeberl / chisel-lab
  Lab exercises for Chisel in the digital electronics 2 course at DTU
  ☆201Updated 2 weeks ago
• ucb-bar / riscv-mini
  Simple RISC-V 3-stage Pipeline in Chisel
  ☆581Updated 10 months ago
• riscv-ovpsim / imperas-riscv-tests
  ☆179Updated last year
• davidepatti / noxim
  Network on Chip Simulator
  ☆276Updated last year
• pulp-platform / cheshire
  A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
  ☆267Updated this week
• SpinalHDL / NaxRiscv
  ☆289Updated 3 months ago