riscv / riscv-bitmanip
Working draft of the proposed RISC-V Bitmanipulation extension
☆203Updated 5 months ago
Related projects: ⓘ
- RISC-V RV64GC emulator designed for RTL co-simulation☆210Updated last week
- Documenting the expected behaviour and supported command-line switches for GNU and LLVM based RISC-V toolchains☆142Updated last week
- ☆150Updated 6 months ago
- RISC-V Torture Test☆163Updated 2 months ago
- Sail RISC-V model☆428Updated this week
- RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)☆305Updated 2 years ago
- RISC-V Processor Trace Specification☆154Updated 2 months ago
- Working Draft of the RISC-V Debug Specification Standard☆454Updated last week
- TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems☆143Updated 2 years ago
- Instruction Set Generator initially contributed by Futurewei☆255Updated 11 months ago
- Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)☆237Updated this week
- ☆154Updated 9 months ago
- RISC-V Debug Support for our PULP RISC-V Cores☆213Updated last month
- ☆501Updated 2 weeks ago
- RiscyOO: RISC-V Out-of-Order Processor☆148Updated 4 years ago
- Common RTL blocks used in SiFive's projects☆177Updated 2 years ago
- Bare Metal Compatibility Library for the Freedom Platform☆154Updated 9 months ago
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆208Updated last month
- ☆98Updated this week
- RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance☆350Updated 11 months ago
- A 256-RISC-V-core system with low-latency access into shared L1 memory.☆263Updated this week
- RISC-V Packed SIMD Extension☆138Updated 10 months ago
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆187Updated last week
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆418Updated last month
- RISC-V CPU Core☆280Updated 3 months ago
- RISC-V Formal Verification Framework☆574Updated 2 years ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆161Updated last month
- RISC-V cryptography extensions standardisation work.☆359Updated 6 months ago
- RISC-V backports for binutils-gdb. Development is done upstream at the FSF.☆147Updated 2 years ago
- Tile based architecture designed for computing efficiency, scalability and generality☆225Updated this week