riscv/riscv-bitmanip external links

---

GitHub - View repository

GitHub.dev - Open in online code editor

Star history - Growth chart over time

deps.dev - Dependencies and security vulnerabilities

Gitingest - Export source code for LLM usage

Repomix - Export source code for LLM usage

uithub - Export source code for LLM usage

Close

riscv/riscv-bitmanip

Readme badge preview -

If you own this repo, copy the snippet below and add it to your README.md

---

Copy

[![RelatedRepos](https://img.shields.io/badge/related-repos-yellow)](https://relatedrepos.com/gh/riscv/riscv-bitmanip)

Close

riscv / riscv-bitmanipView on GitHubMore

• External links
• Readme badge

Working draft of the proposed RISC-V Bitmanipulation extension

☆218Mar 20, 2024Updated 2 years ago

Alternatives and similar repositories for riscv-bitmanip

Users that are interested in riscv-bitmanip are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.

• riscvarchive / riscv-code-size-reduction

  View on GitHub
  ☆148Feb 29, 2024Updated 2 years ago
• riscv-non-isa / riscv-trace-spec

  View on GitHub
  RISC-V Processor Trace Specification
  ☆217Jun 25, 2026Updated last week
• riscv / riscv-profiles

  View on GitHub
  RISC-V Architecture Profiles
  ☆190Apr 22, 2026Updated 2 months ago
• riscv / riscv-p-spec

  View on GitHub
  RISC-V Packed SIMD Extension
  ☆174Jun 28, 2026Updated last week
• riscv / riscv-crypto

  View on GitHub
  RISC-V cryptography extensions standardisation work.
  ☆415Mar 7, 2026Updated 4 months ago
• Wordpress hosting with auto-scaling - Free Trial Offer • Ad
  Fully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
• riscv / riscv-debug-spec

  View on GitHub
  RISC-V Debug Specification Standard
  ☆517Apr 8, 2026Updated 3 months ago
• openhwgroup / cv32e40s

  View on GitHub
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆161Oct 31, 2024Updated last year
• riscv / riscv-arch-test

  View on GitHub
  The RISC-V Architectural Certification Tests (ACTs) are a set of assembly language tests designed to certify that a design faithfully imp…
  ☆737Jun 29, 2026Updated last week
• riscv / riscv-opcodes

  View on GitHub
  RISC-V Opcodes
  ☆865May 20, 2026Updated last month
• riscv / sail-riscv

  View on GitHub
  Sail RISC-V model
  ☆724Jun 30, 2026Updated last week
• riscvarchive / configuration-structure

  View on GitHub
  RISC-V Configuration Structure
  ☆41Oct 30, 2024Updated last year
• riscvarchive / riscv-CMOs

  View on GitHub
  ☆91Aug 26, 2025Updated 10 months ago
• riscv / riscv-plic-spec

  View on GitHub
  PLIC Specification
  ☆154Apr 8, 2026Updated 3 months ago
• riscvarchive / riscv-v-spec

  View on GitHub
  Working draft of the proposed RISC-V V vector extension
  ☆1,085Mar 17, 2024Updated 2 years ago
• Deploy to Railway using AI coding agents - Free Credits Offer • Ad
  Use Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
• riscv / riscv-fast-interrupt

  View on GitHub
  Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
  ☆297Updated this week
• riscvarchive / riscv-zicond

  View on GitHub
  The ISA specification for the ZiCondOps extension.
  ☆19Mar 21, 2024Updated 2 years ago
• riscv-non-isa / riscv-toolchain-conventions

  View on GitHub
  Documenting the expected behaviour and supported command-line switches for GNU and LLVM based RISC-V toolchains
  ☆152Jun 4, 2026Updated last month
• riscv-software-src / riscv-pk

  View on GitHub
  RISC-V Proxy Kernel
  ☆705Oct 2, 2025Updated 9 months ago
• mmicko / cross-fpga

  View on GitHub
  Cross compile FPGA tools
  ☆21Jan 4, 2021Updated 5 years ago
• openhwgroup / cvfpu

  View on GitHub
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆620May 26, 2026Updated last month
• riscv-non-isa / riscv-rvv-intrinsic-doc

  View on GitHub
  ☆377Jun 18, 2026Updated 2 weeks ago
• riscv / riscv-bfloat16

  View on GitHub
  ☆39Mar 6, 2026Updated 4 months ago
• riscv-software-src / riscv-isa-sim

  View on GitHub
  Spike, a RISC-V ISA Simulator
  ☆3,163Jun 26, 2026Updated last week
• Deploy on Railway without the complexity - Free Credits Offer • Ad
  Connect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
• riscvarchive / riscv-eabi-spec

  View on GitHub
  Proposal for new Embedded ABI (EABI) for use in embedded RISC-V systems.
  ☆26Jun 7, 2021Updated 5 years ago
• riscv-collab / riscv-openocd

  View on GitHub
  Fork of OpenOCD that has RISC-V support
  ☆520Jun 23, 2026Updated 2 weeks ago
• riscvarchive / riscv-platform-specs

  View on GitHub
  RISC-V Profiles and Platform Specification
  ☆116Sep 6, 2023Updated 2 years ago
• riscv / riscv-isa-manual

  View on GitHub
  RISC-V Instruction Set Manual
  ☆4,694Updated this week
• cliffordwolf / bextdep

  View on GitHub
  Reference Hardware Implementations of Bit Extract/Deposit Instructions
  ☆24Oct 31, 2017Updated 8 years ago
• pulp-platform / pulp_soc

  View on GitHub
  pulp_soc is the core building component of PULP based SoCs
  ☆84Mar 10, 2025Updated last year
• riscv-software-src / opensbi

  View on GitHub
  RISC-V Open Source Supervisor Binary Interface
  ☆1,497Jul 1, 2026Updated last week
• scarv / xcrypto

  View on GitHub
  XCrypto: a cryptographic ISE for RISC-V
  ☆92Jan 5, 2023Updated 3 years ago
• riscvarchive / riscv-binutils-gdb

  View on GitHub
  RISC-V backports for binutils-gdb. Development is done upstream at the FSF.
  ☆152Jul 7, 2022Updated 4 years ago
• Wordpress hosting with auto-scaling - Free Trial Offer • Ad
  Fully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
• SymbioticEDA / riscv-formal

  View on GitHub
  RISC-V Formal Verification Framework
  ☆633Apr 6, 2022Updated 4 years ago
• openhwgroup / cv32e40x

  View on GitHub
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆274Nov 6, 2024Updated last year
• rems-project / sail

  View on GitHub
  Sail architecture definition language
  ☆904Updated this week
• riscv-software-src / riscv-tests

  View on GitHub
  ☆1,214Jun 3, 2026Updated last month
• ucb-bar / riscv-sodor

  View on GitHub
  educational microarchitectures for risc-v isa
  ☆749Sep 1, 2025Updated 10 months ago
• openhwgroup / cv32e40p

  View on GitHub
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,258May 29, 2026Updated last month
• pulp-platform / snitch

  View on GitHub
  ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!
  ☆230Nov 22, 2023Updated 2 years ago