Alternatives and similar repositories for riscv-bitmanip

Users that are interested in riscv-bitmanip are comparing it to the libraries listed below

• riscvarchive / riscv-code-size-reduction
  ☆147Updated last year
• riscv-non-isa / riscv-trace-spec
  RISC-V Processor Trace Specification
  ☆193Updated last month
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆196Updated last year
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆230Updated 9 months ago
• riscv / riscv-fast-interrupt
  Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
  ☆277Updated last week
• riscv-non-isa / riscv-toolchain-conventions
  Documenting the expected behaviour and supported command-line switches for GNU and LLVM based RISC-V toolchains
  ☆152Updated last week
• bucaps / marss-riscv
  TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems
  ☆157Updated 3 years ago
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆244Updated 10 months ago
• riscv / riscv-debug-spec
  Working Draft of the RISC-V Debug Specification Standard
  ☆494Updated last week
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆161Updated 5 years ago
• bluespec / Piccolo
  RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)
  ☆327Updated 3 years ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆177Updated 4 months ago
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆293Updated last year
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆270Updated 4 months ago
• embench / embench-iot
  The main Embench repository
  ☆288Updated last year
• riscv / riscv-p-spec
  RISC-V Packed SIMD Extension
  ☆151Updated last year
• openhwgroup / programs
  Documentation for the OpenHW Group's set of CORE-V RISC-V cores
  ☆218Updated 3 months ago
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆265Updated 2 weeks ago
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆150Updated 10 months ago
• riscv-ovpsim / imperas-riscv-tests
  ☆187Updated last year
• pulp-platform / snitch
  ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!
  ☆226Updated last year
• ucb-bar / berkeley-hardfloat
  ☆341Updated last year
• pulp-platform / mempool
  A 256-RISC-V-core system with low-latency access into shared L1 memory.
  ☆304Updated last week
• riscv-non-isa / riscv-arch-test
  ☆588Updated 2 weeks ago
• RoaLogic / RV12
  RISC-V CPU Core
  ☆373Updated 2 months ago
• bluespec / Flute
  RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance
  ☆374Updated last year
• chipsalliance / Cores-VeeR-EH2
  ☆244Updated 2 years ago
• riscv / riscv-crypto
  RISC-V cryptography extensions standardisation work.
  ☆395Updated last year
• riscvarchive / riscv-CMOs
  ☆90Updated 2 weeks ago
• SpinalHDL / NaxRiscv
  ☆295Updated last month