riscv-non-isa/riscv-rvv-intrinsic-doc external links

---

GitHub - View repository

GitHub.dev - Open in online code editor

Star history - Growth chart over time

deps.dev - Dependencies and security vulnerabilities

Gitingest - Export source code for LLM usage

Repomix - Export source code for LLM usage

uithub - Export source code for LLM usage

Close

riscv-non-isa/riscv-rvv-intrinsic-doc

Readme badge preview -

If you own this repo, copy the snippet below and add it to your README.md

---

Copy

[![RelatedRepos](https://img.shields.io/badge/related-repos-yellow)](https://relatedrepos.com/gh/riscv-non-isa/riscv-rvv-intrinsic-doc)

Close

riscv-non-isa / riscv-rvv-intrinsic-docView on GitHubMore

• External links
• Readme badge

☆379Aug 26, 2026Updated this week

Alternatives and similar repositories for riscv-rvv-intrinsic-doc

Users that are interested in riscv-rvv-intrinsic-doc are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.

• riscvarchive / riscv-v-spec

  View on GitHub
  Working draft of the proposed RISC-V V vector extension
  ☆1,088Mar 17, 2024Updated 2 years ago
• riscv-non-isa / riscv-toolchain-conventions

  View on GitHub
  Documenting the expected behaviour and supported command-line switches for GNU and LLVM based RISC-V toolchains
  ☆153Aug 18, 2026Updated last week
• chipsalliance / riscv-vector-tests

  View on GitHub
  Unit tests generator for RVV 1.0
  ☆116May 25, 2026Updated 3 months ago
• riscv-non-isa / riscv-c-api-doc

  View on GitHub
  Documentation of the RISC-V C API
  ☆88Aug 18, 2026Updated last week
• RALC88 / riscv-vectorized-benchmark-suite

  View on GitHub
  RiVEC Bencmark Suite
  ☆133Nov 27, 2024Updated last year
• AI Agents on DigitalOcean Gradient AI Platform • Ad
  Build production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
• riscv / riscv-profiles

  View on GitHub
  RISC-V Architecture Profiles
  ☆192Jul 21, 2026Updated last month
• camel-cdr / rvv-bench

  View on GitHub
  A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code
  ☆154Aug 14, 2026Updated 2 weeks ago
• riscv / riscv-p-spec

  View on GitHub
  RISC-V Packed SIMD Extension
  ☆179Updated this week
• pulp-platform / ara

  View on GitHub
  The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …
  ☆539Aug 19, 2026Updated last week
• XUANTIE-RV / riscv-matrix-extension-spec

  View on GitHub
  A matrix extension proposal for AI applications under RISC-V architecture
  ☆187Apr 1, 2026Updated 4 months ago
• plctlab / plct-gem5

  View on GitHub
  upstream: https://github.com/RALC88/gem5
  ☆34May 30, 2023Updated 3 years ago
• riscv / riscv-bfloat16

  View on GitHub
  ☆40Mar 6, 2026Updated 5 months ago
• plctlab / llvm-project

  View on GitHub
  PLCT实验室的 RISC-V V Spec 实现，基于llvm/llvm-project，rkruppe/rvv-llvm 和 https://repo.hca.bsc.es/gitlab/rferrer/llvm-epi-0.8
  ☆161Sep 3, 2025Updated 11 months ago
• riscv / riscv-opcodes

  View on GitHub
  RISC-V Opcodes
  ☆872Aug 24, 2026Updated last week
• Deploy on Railway without the complexity - Free Credits Offer • Ad
  Connect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
• rivosinc / gem5

  View on GitHub
  This is an read-only mirror of the gem5 simulator. The upstream repository is stored in https://gem5.googlesource.com, code reviews shoul…
  ☆11Apr 13, 2026Updated 4 months ago
• UCTECHIP / rocket_chip_vpu

  View on GitHub
  ☆11Jan 9, 2021Updated 5 years ago
• riscv-software-src / riscv-isa-sim

  View on GitHub
  Spike, a RISC-V ISA Simulator
  ☆3,209Updated this week
• compiler-dev / llvm-rv

  View on GitHub
  Full Support 32bit RISC-V in LLVM and CLANG for Vector Extension
  ☆43Dec 21, 2020Updated 5 years ago
• riscvarchive / riscv-code-size-reduction

  View on GitHub
  ☆145Feb 29, 2024Updated 2 years ago
• dzaima / intrinsics-viewer

  View on GitHub
  x86-64, ARM, and RVV intrinsics viewer
  ☆79Jun 18, 2026Updated 2 months ago
• plctlab / rvv-benchmark

  View on GitHub
  PLCT实验室 rvv-llvm 实现配套的 benchmark / testcases
  ☆21Nov 26, 2020Updated 5 years ago
• riscv / riscv-crypto

  View on GitHub
  RISC-V cryptography extensions standardisation work.
  ☆411Mar 7, 2026Updated 5 months ago
• jiegec / rvv-kernels

  View on GitHub
  Implements kernels with RISC-V Vector
  ☆22Mar 24, 2023Updated 3 years ago
• Serverless GPU API endpoints on Runpod - Get Bonus Credits • Ad
  Skip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
• riscv-collab / riscv-gnu-toolchain

  View on GitHub
  GNU toolchain for RISC-V, including GCC
  ☆4,596Updated this week
• riscv / riscv-bitmanip

  View on GitHub
  Working draft of the proposed RISC-V Bitmanipulation extension
  ☆219Mar 20, 2024Updated 2 years ago
• ISRC-CAS / c910-llvm

  View on GitHub
  平头哥玄铁C910的LLVM工具链支持，由PLCT实验室提供，非官方版本
  ☆75Mar 15, 2021Updated 5 years ago
• riscv-non-isa / riscv-asm-manual

  View on GitHub
  RISC-V Assembly Programmer's Manual
  ☆1,636Aug 18, 2026Updated last week
• riscv-non-isa / riscv-elf-psabi-doc

  View on GitHub
  A RISC-V ELF psABI Document
  ☆851Aug 13, 2026Updated 2 weeks ago
• FeddrickAquino / sse2rvv

  View on GitHub
  ☆21Feb 16, 2023Updated 3 years ago
• hushenwei2000 / rvv-atg

  View on GitHub
  RISC-V Vector (RVV) Automatic Tests Generator with full instructions coverage, including self-checking test and signature test (RISC-V Co…
  ☆17Apr 3, 2024Updated 2 years ago
• ic-lab-duth / RISC-V-Vector

  View on GitHub
  Vector processor for RISC-V vector ISA
  ☆145Oct 19, 2020Updated 5 years ago
• riscv-stc / riscv-matrix-spec

  View on GitHub
  RISC-V Matrix Specification
  ☆27Dec 2, 2024Updated last year
• 1-Click AI Models by DigitalOcean Gradient • Ad
  Deploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
• riscv / riscv-arch-test

  View on GitHub
  The RISC-V Architectural Certification Tests (ACTs) are a set of assembly language tests designed to certify that a design faithfully imp…
  ☆777Updated this week
• riscv-ovpsim / imperas-riscv-tests

  View on GitHub
  ☆203Dec 14, 2023Updated 2 years ago
• brucehoult / rvv_example

  View on GitHub
  Simple demonstration of using the RISC-V Vector extension
  ☆51Apr 18, 2024Updated 2 years ago
• riscv / riscv-isa-manual

  View on GitHub
  RISC-V Instruction Set Manual
  ☆4,791Updated this week
• ucb-bar / hwacha

  View on GitHub
  Microarchitecture implementation of the decoupled vector-fetch accelerator
  ☆166Jan 25, 2024Updated 2 years ago
• nibrunie / rvv-examples

  View on GitHub
  Example of RISC-V Vector programming
  ☆31Jul 14, 2026Updated last month
• zhangwm-pt / prebuilt_whl

  View on GitHub
  ☆14Sep 28, 2023Updated 2 years ago