Chisel: A Modern Hardware Design Language
☆4,611Mar 17, 2026Updated this week
Alternatives and similar repositories for chisel
Users that are interested in chisel are comparing it to the libraries listed below
Sorting:
- Rocket Chip Generator☆3,722Feb 25, 2026Updated 3 weeks ago
- Flexible Intermediate Representation for RTL☆749Aug 20, 2024Updated last year
- Generator Bootcamp Material: Learn Chisel the Right Way☆1,117Sep 10, 2024Updated last year
- chisel tutorial exercises and answers☆748Jan 6, 2022Updated 4 years ago
- A template project for beginning new Chisel work☆694Feb 24, 2026Updated 3 weeks ago
- Digital Design with Chisel☆899Mar 13, 2026Updated last week
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,176Mar 8, 2026Updated last week
- Scala based HDL☆1,935Updated this week
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,105Mar 11, 2026Updated last week
- Open-source high-performance RISC-V processor☆6,904Updated this week
- Verilator open-source SystemVerilog simulator and lint system☆3,439Updated this week
- Circuit IR Compilers and Tools☆2,065Updated this week
- educational microarchitectures for risc-v isa☆740Sep 1, 2025Updated 6 months ago
- The batteries-included testing and formal verification library for Chisel-based RTL designs.☆233Aug 19, 2024Updated last year
- Simple RISC-V 3-stage Pipeline in Chisel☆603Aug 9, 2024Updated last year
- FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility☆1,001Mar 9, 2026Updated last week
- Yosys Open SYnthesis Suite☆4,333Updated this week
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,063Feb 11, 2026Updated last month
- A Library of Chisel3 Tools for Digital Signal Processing☆245Apr 29, 2024Updated last year
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,845Mar 10, 2026Updated last week
- PicoRV32 - A Size-Optimized RISC-V CPU☆4,024Jun 27, 2024Updated last year
- Spike, a RISC-V ISA Simulator☆3,034Feb 26, 2026Updated 3 weeks ago
- Berkeley's Spatial Array Generator☆1,251Updated this week
- Chisel examples and code snippets☆271Aug 1, 2022Updated 3 years ago
- Chisel/Firrtl execution engine☆155Aug 21, 2024Updated last year
- RISC-V Instruction Set Manual☆4,529Updated this week
- Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2☆2,827Mar 24, 2021Updated 4 years ago
- Provides various testers for chisel users☆101Jan 12, 2023Updated 3 years ago
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,789Mar 13, 2026Updated last week
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,797Feb 17, 2026Updated last month
- Icarus Verilog☆3,377Mar 10, 2026Updated last week
- Build your hardware, easily!☆3,773Updated this week
- cocotb: Python-based chip (RTL) verification☆2,284Mar 13, 2026Updated last week
- ☆368Sep 12, 2025Updated 6 months ago
- Package manager and build abstraction tool for FPGA/ASIC development☆1,396Feb 13, 2026Updated last month
- GNU toolchain for RISC-V, including GCC☆4,394Mar 13, 2026Updated last week
- RISC-V SoC designed by students in UCAS☆1,516Jan 14, 2026Updated 2 months ago
- VeeR EH1 core☆930May 29, 2023Updated 2 years ago
- Random instruction generator for RISC-V processor verification☆1,262Mar 5, 2026Updated 2 weeks ago