chipsalliance / chiselLinks
Chisel: A Modern Hardware Design Language
☆4,562Updated this week
Alternatives and similar repositories for chisel
Users that are interested in chisel are comparing it to the libraries listed below
Sorting:
- Rocket Chip Generator☆3,669Updated 3 weeks ago
- Scala based HDL☆1,913Updated last week
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,067Updated 2 weeks ago
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,128Updated last week
- A FPGA friendly 32 bit RISC-V CPU implementation☆2,999Updated last month
- Generator Bootcamp Material: Learn Chisel the Right Way☆1,107Updated last year
- Verilator open-source SystemVerilog simulator and lint system☆3,324Updated last week
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,791Updated this week
- Digital Design with Chisel☆893Updated 2 months ago
- chisel tutorial exercises and answers☆743Updated 4 years ago
- Circuit IR Compilers and Tools☆2,025Updated this week
- Flexible Intermediate Representation for RTL☆747Updated last year
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,751Updated last week
- Spike, a RISC-V ISA Simulator☆3,011Updated last week
- opensouce RISC-V cpu core implemented in Verilog from scratch in one night!☆2,485Updated last month
- RISC-V Tools (ISA Simulator and Tests)☆1,174Updated 3 years ago
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,762Updated last month
- A template project for beginning new Chisel work☆689Updated last week
- Yosys Open SYnthesis Suite☆4,261Updated this week
- FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility☆994Updated this week
- educational microarchitectures for risc-v isa☆732Updated 5 months ago
- ☆1,877Updated this week
- Working draft of the proposed RISC-V V vector extension☆1,067Updated last year
- PicoRV32 - A Size-Optimized RISC-V CPU☆3,928Updated last year
- ☆1,117Updated 2 weeks ago
- RISC-V CPU Core (RV32IM)☆1,633Updated 4 years ago
- cocotb: Python-based chip (RTL) verification☆2,248Updated this week
- A small, light weight, RISC CPU soft core☆1,504Updated last month
- The Ultra-Low Power RISC-V Core☆1,725Updated 6 months ago
- OpenXuantie - OpenC910 Core☆1,387Updated last year