chipsalliance / chiselLinks
Chisel: A Modern Hardware Design Language
☆4,505Updated this week
Alternatives and similar repositories for chisel
Users that are interested in chisel are comparing it to the libraries listed below
Sorting:
- Rocket Chip Generator☆3,640Updated 3 months ago
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,031Updated last week
- Scala based HDL☆1,893Updated this week
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,069Updated 2 weeks ago
- A FPGA friendly 32 bit RISC-V CPU implementation☆2,939Updated last week
- Verilator open-source SystemVerilog simulator and lint system☆3,233Updated this week
- Generator Bootcamp Material: Learn Chisel the Right Way☆1,090Updated last year
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,722Updated last week
- Spike, a RISC-V ISA Simulator☆2,961Updated this week
- Digital Design with Chisel☆882Updated 3 weeks ago
- chisel tutorial exercises and answers☆739Updated 3 years ago
- opensouce RISC-V cpu core implemented in Verilog from scratch in one night!☆2,454Updated 5 months ago
- PicoRV32 - A Size-Optimized RISC-V CPU☆3,830Updated last year
- Flexible Intermediate Representation for RTL☆749Updated last year
- FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility☆980Updated 6 months ago
- A small, light weight, RISC CPU soft core☆1,485Updated last week
- Icarus Verilog☆3,253Updated last week
- RISC-V Tools (ISA Simulator and Tests)☆1,171Updated 2 years ago
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,704Updated 2 weeks ago
- Yosys Open SYnthesis Suite☆4,174Updated last week
- cocotb: Python-based chip (RTL) verification☆2,175Updated last week
- Circuit IR Compilers and Tools☆1,975Updated this week
- OpenXuantie - OpenC910 Core☆1,357Updated last year
- Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro☆1,028Updated last week
- A template project for beginning new Chisel work☆674Updated 2 months ago
- SERV - The SErial RISC-V CPU☆1,707Updated last week
- Working draft of the proposed RISC-V V vector extension☆1,056Updated last year
- 🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independe…☆1,930Updated this week
- The Ultra-Low Power RISC-V Core☆1,672Updated 4 months ago
- educational microarchitectures for risc-v isa☆727Updated 3 months ago