Alternatives and similar repositories for riscv-code-size-reduction

Users that are interested in riscv-code-size-reduction are comparing it to the libraries listed below

• riscv-non-isa / riscv-trace-spec
  RISC-V Processor Trace Specification
  ☆182Updated 2 weeks ago
• riscv / riscv-fast-interrupt
  Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
  ☆268Updated this week
• riscv-non-isa / riscv-toolchain-conventions
  Documenting the expected behaviour and supported command-line switches for GNU and LLVM based RISC-V toolchains
  ☆151Updated last week
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆229Updated 6 months ago
• riscv / riscv-CMOs
  ☆86Updated 3 years ago
• riscv / riscv-bitmanip
  Working draft of the proposed RISC-V Bitmanipulation extension
  ☆211Updated last year
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆146Updated 7 months ago
• bucaps / marss-riscv
  TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems
  ☆152Updated 3 years ago
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆238Updated 6 months ago
• riscv / riscv-p-spec
  RISC-V Packed SIMD Extension
  ☆146Updated last year
• openhwgroup / programs
  Documentation for the OpenHW Group's set of CORE-V RISC-V cores
  ☆214Updated last week
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆195Updated 10 months ago
• riscv-non-isa / riscv-iommu
  RISC-V IOMMU Specification
  ☆118Updated 3 weeks ago
• riscv-ovpsim / imperas-riscv-tests
  ☆175Updated last year
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆156Updated 4 years ago
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆257Updated 2 weeks ago
• riscv / riscv-aia
  ☆89Updated 2 months ago
• riscv / riscv-plic-spec
  PLIC Specification
  ☆140Updated 2 years ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆174Updated 3 weeks ago
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆284Updated last year
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆257Updated last month
• riscv / riscv-profiles
  RISC-V Architecture Profiles
  ☆150Updated 3 months ago
• chipsalliance / VeeR-ISS
  ☆135Updated last year
• litmus-tests / litmus-tests-riscv
  RISC-V architecture concurrency model litmus tests
  ☆78Updated last week
• embench / embench-iot
  The main Embench repository
  ☆281Updated 9 months ago
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆108Updated last week
• riscv-software-src / riscof
  ☆80Updated 2 months ago
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆114Updated 3 years ago
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆68Updated 10 months ago
• riscv-non-isa / riscv-c-api-doc
  Documentation of the RISC-V C API
  ☆76Updated 3 weeks ago