RISC-V Instruction Set Manual
☆4,521Mar 6, 2026Updated this week
Alternatives and similar repositories for riscv-isa-manual
Users that are interested in riscv-isa-manual are comparing it to the libraries listed below
Sorting:
- Spike, a RISC-V ISA Simulator☆3,028Feb 26, 2026Updated last week
- GNU toolchain for RISC-V, including GCC☆4,386Feb 13, 2026Updated 3 weeks ago
- RISC-V Assembly Programmer's Manual☆1,615Feb 26, 2026Updated last week
- RISC-V Opcodes☆842Updated this week
- RISC-V Tools (ISA Simulator and Tests)☆1,181Dec 22, 2022Updated 3 years ago
- Working draft of the proposed RISC-V V vector extension☆1,072Mar 17, 2024Updated last year
- Chisel: A Modern Hardware Design Language☆4,598Feb 28, 2026Updated last week
- RISC-V Proxy Kernel☆687Oct 2, 2025Updated 5 months ago
- Rocket Chip Generator☆3,705Feb 25, 2026Updated last week
- Working Draft of the RISC-V Debug Specification Standard☆505Mar 1, 2026Updated last week
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,090Feb 5, 2026Updated last month
- RISC-V Open Source Supervisor Binary Interface☆1,396Feb 25, 2026Updated last week
- Open-source high-performance RISC-V processor☆6,885Updated this week
- A RISC-V ELF psABI Document☆836Updated this week
- ☆1,133Jan 22, 2026Updated last month
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,837Updated this week
- ☆652Updated this week
- Xv6 for RISC-V☆9,277Dec 17, 2025Updated 2 months ago
- PicoRV32 - A Size-Optimized RISC-V CPU☆3,986Jun 27, 2024Updated last year
- Verilator open-source SystemVerilog simulator and lint system☆3,391Updated this week
- Documentation for the RISC-V Supervisor Binary Interface☆456Updated this week
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,048Feb 11, 2026Updated 3 weeks ago
- Sail RISC-V model☆672Updated this week
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,160Updated this week
- RISC-V Linux Port☆607Apr 12, 2019Updated 6 years ago
- Random instruction generator for RISC-V processor verification☆1,259Updated this week
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,785Feb 17, 2026Updated 2 weeks ago
- ☆373May 22, 2023Updated 2 years ago
- Documentation developer guide☆128Updated this week
- The Ultra-Low Power RISC-V Core☆1,748Aug 6, 2025Updated 7 months ago
- opensouce RISC-V cpu core implemented in Verilog from scratch in one night!☆2,498Jan 7, 2026Updated 2 months ago
- Fork of OpenOCD that has RISC-V support☆511Oct 9, 2025Updated 5 months ago
- Icarus Verilog☆3,352Updated this week
- Official QEMU mirror. Please see https://www.qemu.org/contribute/ for how to submit changes to QEMU. Pull Requests are disabled. Please o…☆12,806Updated this week
- Yosys Open SYnthesis Suite☆4,316Updated this week
- RISC-V Processor Trace Specification☆208Feb 27, 2026Updated last week
- Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2☆2,815Mar 24, 2021Updated 4 years ago
- Digital Design with Chisel☆899Feb 26, 2026Updated last week
- educational microarchitectures for risc-v isa☆741Sep 1, 2025Updated 6 months ago