riscv / riscv-isa-manualView external linksLinks
RISC-V Instruction Set Manual
☆4,496Updated this week
Alternatives and similar repositories for riscv-isa-manual
Users that are interested in riscv-isa-manual are comparing it to the libraries listed below
Sorting:
- Spike, a RISC-V ISA Simulator☆3,020Updated this week
- GNU toolchain for RISC-V, including GCC☆4,364Updated this week
- RISC-V Assembly Programmer's Manual☆1,606Feb 10, 2026Updated last week
- RISC-V Opcodes☆836Updated this week
- RISC-V Tools (ISA Simulator and Tests)☆1,175Dec 22, 2022Updated 3 years ago
- Working draft of the proposed RISC-V V vector extension☆1,069Mar 17, 2024Updated last year
- Chisel: A Modern Hardware Design Language☆4,567Updated this week
- RISC-V Proxy Kernel☆688Oct 2, 2025Updated 4 months ago
- Rocket Chip Generator☆3,677Jan 9, 2026Updated last month
- Working Draft of the RISC-V Debug Specification Standard☆504Feb 5, 2026Updated last week
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,072Feb 5, 2026Updated last week
- RISC-V Open Source Supervisor Binary Interface☆1,370Jan 8, 2026Updated last month
- Open-source high-performance RISC-V processor☆6,873Updated this week
- ☆1,119Jan 22, 2026Updated 3 weeks ago
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,797Feb 10, 2026Updated last week
- A RISC-V ELF psABI Document☆831Feb 6, 2026Updated last week
- ☆650Updated this week
- Xv6 for RISC-V☆9,217Dec 17, 2025Updated 2 months ago
- PicoRV32 - A Size-Optimized RISC-V CPU☆3,945Jun 27, 2024Updated last year
- Verilator open-source SystemVerilog simulator and lint system☆3,356Updated this week
- Documentation for the RISC-V Supervisor Binary Interface☆454Feb 6, 2026Updated last week
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,008Dec 15, 2025Updated 2 months ago
- Sail RISC-V model☆667Updated this week
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,138Updated this week
- RISC-V Linux Port☆608Apr 12, 2019Updated 6 years ago
- Random instruction generator for RISC-V processor verification☆1,252Oct 1, 2025Updated 4 months ago
- ☆373May 22, 2023Updated 2 years ago
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,764Updated this week
- Documentation developer guide☆125Feb 9, 2026Updated last week
- The Ultra-Low Power RISC-V Core☆1,733Aug 6, 2025Updated 6 months ago
- opensouce RISC-V cpu core implemented in Verilog from scratch in one night!☆2,489Jan 7, 2026Updated last month
- Fork of OpenOCD that has RISC-V support☆509Oct 9, 2025Updated 4 months ago
- Icarus Verilog☆3,324Feb 9, 2026Updated last week
- Official QEMU mirror. Please see https://www.qemu.org/contribute/ for how to submit changes to QEMU. Pull Requests are ignored. Please on…☆12,679Feb 10, 2026Updated last week
- Yosys Open SYnthesis Suite☆4,286Updated this week
- RISC-V Processor Trace Specification☆207Feb 9, 2026Updated last week
- Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2☆2,811Mar 24, 2021Updated 4 years ago
- Digital Design with Chisel☆895Updated this week
- educational microarchitectures for risc-v isa☆737Sep 1, 2025Updated 5 months ago