GPGPU processor supporting RISCV-V extension, developed with Chisel HDL
☆955Aug 18, 2026Updated last month
Alternatives and similar repositories for ventus-gpgpu
Users that are interested in ventus-gpgpu are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆2,269Updated this week
- GPGPU supporting RISCV-V, developed with verilog HDL☆171Feb 24, 2025Updated last year
- Ventus GPGPU ISA Simulator Based on Spike☆56Sep 3, 2026Updated 3 weeks ago
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆548Updated this week
- Open-source high-performance RISC-V processor☆7,274Updated this week
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- An open source GPU based off of the AMD Southern Islands ISA.☆1,415Aug 18, 2025Updated last year
- GPGPU microprocessor architecture☆2,224Nov 8, 2024Updated last year
- OpenSource GPU, in Verilog, loosely based on RISC-V ISA☆1,380Nov 22, 2024Updated last year
- Berkeley's Spatial Array Generator☆1,481Updated this week
- OpenXuantie - OpenC910 Core☆1,478Jun 28, 2024Updated 2 years ago
- ☆145May 23, 2024Updated 2 years ago
- ☆250Jun 25, 2025Updated last year
- How to make undergraduates or new graduates ready for advanced computer architecture research or modern CPU design☆672Aug 13, 2024Updated 2 years ago
- A matrix extension proposal for AI applications under RISC-V architecture☆188Apr 1, 2026Updated 5 months ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆36May 17, 2026Updated 4 months ago
- GPGPU-Sim provides a detailed simulation model of contemporary NVIDIA GPUs running CUDA and/or OpenCL workloads. It includes support for…☆1,725Feb 15, 2025Updated last year
- A fork of Xiangshan for AI☆57Updated this week
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,241Sep 11, 2026Updated last week
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,395Updated this week
- This is the top-level repository for the Accel-Sim framework.☆679Aug 26, 2026Updated 3 weeks ago
- ☆241Aug 22, 2026Updated last month
- 体系结构研讨 + ysyx高阶大纲 (WIP☆218Oct 14, 2024Updated last year
- The Ultra-Low Power RISC-V Core☆1,923Aug 6, 2025Updated last year
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- Digital Design with Chisel☆940Updated this week
- RISC-V SoC designed by students in UCAS☆1,552Updated this week
- A Chisel RTL generator for network-on-chip interconnects☆237Nov 7, 2025Updated 10 months ago
- Simple RISC-V 3-stage Pipeline in Chisel☆619Aug 9, 2024Updated 2 years ago
- ☆324Jul 22, 2026Updated 2 months ago
- Rocket Chip Generator☆3,869Sep 13, 2026Updated last week
- FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation☆122May 11, 2023Updated 3 years ago
- A machine learning accelerator core designed for energy-efficient AI at the edge.☆2,577Updated this week
- LLVM OpenCL C compiler suite for ventus GPGPU☆65Sep 3, 2026Updated 3 weeks ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆212Jun 25, 2020Updated 6 years ago
- Chisel: A Modern Hardware Design Language☆4,788Updated this week
- A template project for beginning new Chisel work☆708Feb 24, 2026Updated 6 months ago
- ☆84Jun 1, 2022Updated 4 years ago
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆3,128Updated this week
- Modern co-simulation framework for RISC-V CPUs☆184Updated this week
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆166Jan 25, 2024Updated 2 years ago