GPGPU processor supporting RISCV-V extension, developed with Chisel HDL
☆957Oct 13, 2026Updated this week
Alternatives and similar repositories for ventus-gpgpu
Users that are interested in ventus-gpgpu are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆2,313Updated this week
- GPGPU supporting RISCV-V, developed with verilog HDL☆171Feb 24, 2025Updated last year
- Ventus GPGPU ISA Simulator Based on Spike☆56Updated this week
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆551Updated this week
- Open-source high-performance RISC-V processor☆7,306Updated this week
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- An open source GPU based off of the AMD Southern Islands ISA.☆1,426Aug 18, 2025Updated last year
- GPGPU microprocessor architecture☆2,228Nov 8, 2024Updated last year
- OpenSource GPU, in Verilog, loosely based on RISC-V ISA☆1,392Nov 22, 2024Updated last year
- Berkeley's Spatial Array Generator☆1,507Updated this week
- OpenXuantie - OpenC910 Core☆1,479Jun 28, 2024Updated 2 years ago
- ☆145May 23, 2024Updated 2 years ago
- ☆254Jun 25, 2025Updated last year
- How to make undergraduates or new graduates ready for advanced computer architecture research or modern CPU design☆674Aug 13, 2024Updated 2 years ago
- A matrix extension proposal for AI applications under RISC-V architecture☆187Apr 1, 2026Updated 6 months ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆36May 17, 2026Updated 4 months ago
- GPGPU-Sim provides a detailed simulation model of contemporary NVIDIA GPUs running CUDA and/or OpenCL workloads. It includes support for…☆1,749Oct 3, 2026Updated last week
- A fork of Xiangshan for AI☆60Updated this week
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,259Updated this week
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,420Updated this week
- This is the top-level repository for the Accel-Sim framework.☆707Aug 26, 2026Updated last month
- ☆241Aug 22, 2026Updated last month
- 体系结构研讨 + ysyx高阶大纲 (WIP☆220Sep 24, 2026Updated 2 weeks ago
- The Ultra-Low Power RISC-V Core☆1,938Sep 25, 2026Updated 2 weeks ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Digital Design with Chisel☆940Oct 5, 2026Updated last week
- RISC-V SoC designed by students in UCAS☆1,560Sep 22, 2026Updated 3 weeks ago
- A Chisel RTL generator for network-on-chip interconnects☆237Nov 7, 2025Updated 11 months ago
- Simple RISC-V 3-stage Pipeline in Chisel☆620Aug 9, 2024Updated 2 years ago
- ☆324Jul 22, 2026Updated 2 months ago
- Rocket Chip Generator☆3,885Sep 13, 2026Updated last month
- FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation☆123May 11, 2023Updated 3 years ago
- A machine learning accelerator core designed for energy-efficient AI at the edge.☆2,596Updated this week
- LLVM OpenCL C compiler suite for ventus GPGPU☆64Updated this week
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆212Jun 25, 2020Updated 6 years ago
- Chisel: A Modern Hardware Design Language☆4,808Updated this week
- A template project for beginning new Chisel work☆708Feb 24, 2026Updated 7 months ago
- ☆84Jun 1, 2022Updated 4 years ago
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆3,157Updated this week
- Modern co-simulation framework for RISC-V CPUs☆187Updated this week
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆166Jan 25, 2024Updated 2 years ago