GPGPU processor supporting RISCV-V extension, developed with Chisel HDL
☆896May 3, 2026Updated this week
Alternatives and similar repositories for ventus-gpgpu
Users that are interested in ventus-gpgpu are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆1,996Updated this week
- GPGPU supporting RISCV-V, developed with verilog HDL☆148Feb 24, 2025Updated last year
- Ventus GPGPU ISA Simulator Based on Spike☆51Updated this week
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆515Apr 24, 2026Updated last week
- An open source GPU based off of the AMD Southern Islands ISA.☆1,369Aug 18, 2025Updated 8 months ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Open-source high-performance RISC-V processor☆6,996Updated this week
- GPGPU microprocessor architecture☆2,189Nov 8, 2024Updated last year
- OpenSource GPU, in Verilog, loosely based on RISC-V ISA☆1,309Nov 22, 2024Updated last year
- ☆143May 23, 2024Updated last year
- How to make undergraduates or new graduates ready for advanced computer architecture research or modern CPU design☆636Aug 13, 2024Updated last year
- ☆231Jun 25, 2025Updated 10 months ago
- Berkeley's Spatial Array Generator☆1,294Mar 29, 2026Updated last month
- OpenXuantie - OpenC910 Core☆1,430Jun 28, 2024Updated last year
- A matrix extension proposal for AI applications under RISC-V architecture☆181Apr 1, 2026Updated last month
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,234Updated this week
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆33Updated this week
- GPGPU-Sim provides a detailed simulation model of contemporary NVIDIA GPUs running CUDA and/or OpenCL workloads. It includes support for…☆1,630Feb 15, 2025Updated last year
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,148Mar 11, 2026Updated last month
- ☆221Feb 6, 2026Updated 2 months ago
- 体系结构研讨 + ysyx高阶大纲 (WIP☆209Oct 14, 2024Updated last year
- Digital Design with Chisel☆914Updated this week
- RISC-V SoC designed by students in UCAS☆1,525Apr 28, 2026Updated last week
- The Ultra-Low Power RISC-V Core☆1,825Aug 6, 2025Updated 9 months ago
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- A Chisel RTL generator for network-on-chip interconnects☆230Nov 7, 2025Updated 5 months ago
- This is the top-level repository for the Accel-Sim framework.☆596Mar 24, 2026Updated last month
- Simple RISC-V 3-stage Pipeline in Chisel☆607Aug 9, 2024Updated last year
- Rocket Chip Generator☆3,757Apr 21, 2026Updated 2 weeks ago
- LLVM OpenCL C compiler suite for ventus GPGPU☆63Apr 28, 2026Updated last week
- ☆314Updated this week
- FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation☆117May 11, 2023Updated 2 years ago
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆208Jun 25, 2020Updated 5 years ago
- Chisel implementation of Neural Processing Unit for System on the Chip☆29Apr 22, 2026Updated last week
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- A template project for beginning new Chisel work☆696Feb 24, 2026Updated 2 months ago
- Chisel: A Modern Hardware Design Language☆4,650Updated this week
- Modern co-simulation framework for RISC-V CPUs☆174Updated this week
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆166Jan 25, 2024Updated 2 years ago
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,913Updated this week
- A Fast, Low-Overhead On-chip Network☆288Updated this week
- documentation for ventus gpgpu☆20Mar 25, 2025Updated last year