Alternatives and similar repositories for RISC-V-Vector

Users that are interested in RISC-V-Vector are comparing it to the libraries listed below

• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆208Updated 5 months ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆265Updated last week
• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆197Updated 3 years ago
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆226Updated 3 months ago
• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆187Updated last year
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆192Updated last week
• agalimberti / NoCRouter
  RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni
  ☆144Updated 7 years ago
• airin711 / Verilog-caches
  Various caches written in Verilog-HDL
  ☆127Updated 10 years ago
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆195Updated this week
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆98Updated 2 months ago
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆223Updated 5 years ago
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆109Updated 4 years ago
• nishthaparashar / Floating-Point-ALU-in-Verilog
  32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.
  ☆99Updated 6 years ago
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆76Updated 2 years ago
• pulp-platform / fpu
  ☆58Updated 6 years ago
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆138Updated last week
• danshanley / FPU
  IEEE 754 floating point unit in Verilog
  ☆149Updated 9 years ago
• bakhshalipour / NoC-Verilog
  A verilog implementation for Network-on-Chip
  ☆81Updated 8 years ago
• Lampro-Mellon / LM-RISCV-DV
  An Open-Source Design and Verification Environment for RISC-V
  ☆86Updated 4 years ago
• riscv-ovpsim / imperas-riscv-tests
  ☆193Updated 2 years ago
• amonemi / ProNoC
  Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).
  ☆62Updated last month
• ananthbhat94 / DDR4MemoryController
  HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.
  ☆85Updated 7 years ago
• lowRISC / ariane
  Ariane is a 6-stage RISC-V CPU
  ☆153Updated 6 years ago
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆160Updated last year
• RV-BOSC / OpenNoC
  ☆220Updated 7 months ago
• jasonlin316 / RISC-V-CPU
  A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.
  ☆145Updated 6 years ago
• pulp-platform / common_verification
  SystemVerilog modules and classes commonly used for verification
  ☆57Updated last month
• Chainsaw-Team / Chainsaw
  a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…
  ☆67Updated 2 years ago
• adki / gen_amba
  AMBA bus generator including AXI, AHB, and APB
  ☆119Updated 4 years ago
• cnrv / CNRV-FPU
  Basic floating-point components for RISC-V processors
  ☆67Updated 6 years ago