Vector processor for RISC-V vector ISA
☆147Oct 19, 2020Updated 6 years ago
Alternatives and similar repositories for RISC-V-Vector
Users that are interested in RISC-V-Vector are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- 256-bit vector processor based on the RISC-V vector (V) extension☆33May 1, 2021Updated 5 years ago
- DUTH RISC-V Superscalar Microprocessor☆35Oct 23, 2024Updated 2 years ago
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆560Oct 16, 2026Updated last week
- RISC-V Zve32x Vector Coprocessor☆224Jan 22, 2026Updated 9 months ago
- DUTH RISC-V Microprocessor☆26Apr 5, 2026Updated 6 months ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Jan 19, 2021Updated 5 years ago
- RiVEC Bencmark Suite☆134Nov 27, 2024Updated last year
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆68Dec 19, 2021Updated 4 years ago
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆239Aug 25, 2020Updated 6 years ago
- Unit tests generator for RVV 1.0☆118May 25, 2026Updated 5 months ago
- Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit☆39Dec 23, 2021Updated 4 years ago
- SCARV: a side-channel hardened RISC-V platform☆28Jan 11, 2023Updated 3 years ago
- The RTL source for AnyCore RISC-V☆33Mar 18, 2022Updated 4 years ago
- A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code☆155Aug 14, 2026Updated 2 months ago
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- Andes Vector Extension support added to riscv-dv☆19May 29, 2020Updated 6 years ago
- ☆324Jul 22, 2026Updated 3 months ago
- Working draft of the proposed RISC-V V vector extension☆1,088Mar 17, 2024Updated 2 years ago
- GPGPU processor supporting RISCV-V extension, developed with Chisel HDL☆969Updated this week
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆166Jan 25, 2024Updated 2 years ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆35Jun 22, 2024Updated 2 years ago
- Open-source non-blocking L2 cache☆65Updated this week
- VeeR EH2 core☆283Oct 6, 2026Updated 3 weeks ago
- Chisel RISC-V Vector 1.0 Implementation☆159Updated this week
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- VeeR EL2 Core☆349Updated this week
- A RISC-V core running Debian (and a LoongArch core running Linux).☆24Nov 24, 2025Updated 11 months ago
- Ocelot: The Berkeley Out-of-Order Machine With V-EXT support☆264Oct 12, 2026Updated 2 weeks ago
- ☆16Jul 16, 2026Updated 3 months ago
- A simple superscalar out-of-order RISC-V microprocessor☆257Feb 24, 2025Updated last year
- A matrix extension proposal for AI applications under RISC-V architecture☆190Apr 1, 2026Updated 6 months ago
- Instruction Set Generator initially contributed by Futurewei☆322Oct 17, 2023Updated 3 years ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,317Oct 20, 2026Updated last week
- A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.☆153Dec 2, 2019Updated 6 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Chisel implementation of Neural Processing Unit for System on the Chip☆39Oct 15, 2026Updated 2 weeks ago
- ☆204Dec 14, 2023Updated 2 years ago
- Heterogeneous Cluster Interconnect to bind special-purpose HW accelerators with general-purpose cluster cores☆17Oct 14, 2026Updated 2 weeks ago
- 32-bit Superscalar RISC-V CPU☆1,325Sep 18, 2021Updated 5 years ago
- ☆381Oct 15, 2026Updated 2 weeks ago
- Procyon is the brightest star in the constellation of Canis Minor. But it's also the name of my RISC-V out-of-order processor.☆12Apr 6, 2023Updated 3 years ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆192Apr 4, 2026Updated 6 months ago