ic-lab-duth / RISC-V-VectorLinks
Vector processor for RISC-V vector ISA
☆130Updated 5 years ago
Alternatives and similar repositories for RISC-V-Vector
Users that are interested in RISC-V-Vector are comparing it to the libraries listed below
Sorting:
- A Fast, Low-Overhead On-chip Network☆232Updated 2 weeks ago
- An AXI4 crossbar implementation in SystemVerilog☆178Updated 2 months ago
- Network on Chip Implementation written in SytemVerilog☆193Updated 3 years ago
- A Chisel RTL generator for network-on-chip interconnects☆218Updated this week
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆179Updated 11 months ago
- Verilog Configurable Cache☆185Updated last week
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆133Updated 7 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆92Updated this week
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆186Updated last month
- IEEE 754 floating point unit in Verilog☆148Updated 9 years ago
- A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.☆138Updated 5 years ago
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆218Updated 5 years ago
- Various caches written in Verilog-HDL☆128Updated 10 years ago
- AXI4 and AXI4-Lite interface definitions☆97Updated 5 years ago
- Pure digital components of a UCIe controller☆75Updated last week
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆59Updated this week
- Generic Register Interface (contains various adapters)☆133Updated 3 weeks ago
- An Open-Source Design and Verification Environment for RISC-V☆85Updated 4 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆73Updated 10 months ago
- ☆105Updated this week
- RISC-V Verification Interface☆112Updated last week
- A verilog implementation for Network-on-Chip☆77Updated 7 years ago
- Advanced Architecture Labs with CVA6☆70Updated last year
- A dynamic verification library for Chisel.☆157Updated last year
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆94Updated 6 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆82Updated 7 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆105Updated 5 years ago
- ☆204Updated 4 months ago
- Basic floating-point components for RISC-V processors☆66Updated 5 years ago