ic-lab-duth / RISC-V-Vector
Vector processor for RISC-V vector ISA
☆116Updated 4 years ago
Alternatives and similar repositories for RISC-V-Vector:
Users that are interested in RISC-V-Vector are comparing it to the libraries listed below
- A Fast, Low-Overhead On-chip Network☆182Updated this week
- A Chisel RTL generator for network-on-chip interconnects☆189Updated last week
- An AXI4 crossbar implementation in SystemVerilog☆138Updated last month
- Network on Chip Implementation written in SytemVerilog☆171Updated 2 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆163Updated 4 months ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆139Updated 2 weeks ago
- AXI4 and AXI4-Lite interface definitions☆93Updated 4 years ago
- ☆88Updated last year
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆51Updated 3 years ago
- Verilog Configurable Cache☆174Updated 3 months ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆68Updated last week
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆62Updated 3 months ago
- A Style Guide for the Chisel Hardware Construction Language☆107Updated 3 years ago
- Unit tests generator for RVV 1.0☆79Updated this week
- RISC-V Verification Interface☆85Updated last month
- A dynamic verification library for Chisel.☆147Updated 4 months ago
- ☆131Updated last month
- Advanced Architecture Labs with CVA6☆54Updated last year
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆59Updated last year
- AXI Adapter(s) for RISC-V Atomic Operations☆62Updated 6 months ago
- Generic Register Interface (contains various adapters)☆111Updated 5 months ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆93Updated 4 years ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆135Updated this week
- Pure digital components of a UCIe controller☆57Updated last week
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆82Updated 5 years ago
- HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…☆92Updated last year
- SystemVerilog modules and classes commonly used for verification☆46Updated 2 months ago
- General Purpose AXI Direct Memory Access☆49Updated 10 months ago
- Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)☆54Updated last year
- Some useful documents of Synopsys☆67Updated 3 years ago