tenstorrent / riscv-ocelot
Ocelot: The Berkeley Out-of-Order Machine With V-EXT support
☆148Updated last week
Related projects: ⓘ
- Tile based architecture designed for computing efficiency, scalability and generality☆225Updated this week
- RISC-V RV64GC emulator designed for RTL co-simulation☆210Updated last week
- ☆115Updated 11 months ago
- Vector Acceleration IP core for RISC-V*☆130Updated this week
- ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!☆218Updated 9 months ago
- Self checking RISC-V directed tests☆75Updated this week
- A Chisel RTL generator for network-on-chip interconnects☆162Updated 3 weeks ago
- Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model☆130Updated 3 weeks ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆161Updated last month
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆93Updated last year
- Instruction Set Generator initially contributed by Futurewei☆255Updated 11 months ago
- A dynamic verification library for Chisel.☆138Updated 3 months ago
- A Style Guide for the Chisel Hardware Construction Language☆106Updated 3 years ago
- RiscyOO: RISC-V Out-of-Order Processor☆148Updated 4 years ago
- eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V☆140Updated this week
- TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems☆143Updated 2 years ago
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆146Updated 7 months ago
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆179Updated this week
- RISC-V Torture Test☆163Updated 2 months ago
- Verilog Configurable Cache☆165Updated 3 weeks ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆418Updated last month
- VeeR EL2 Core☆243Updated this week
- ☆285Updated last week
- ☆154Updated 9 months ago
- Lectures for the Agile Hardware Design course in Jupyter Notebooks☆78Updated 5 months ago
- CORE-V Family of RISC-V Cores☆199Updated 7 months ago
- ☆257Updated 3 weeks ago
- CVA6 SDK containing RISC-V tools and Buildroot☆59Updated 2 months ago
- Chisel Learning Journey☆105Updated last year
- Modeling Architectural Platform☆156Updated this week