RISC-V Tools (ISA Simulator and Tests)
☆1,195Dec 22, 2022Updated 3 years ago
Alternatives and similar repositories for riscv-tools
Users that are interested in riscv-tools are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- GNU toolchain for RISC-V, including GCC☆4,614Aug 27, 2026Updated 3 weeks ago
- Spike, a RISC-V ISA Simulator☆3,233Updated this week
- RISC-V Linux Port☆607Apr 12, 2019Updated 7 years ago
- Rocket Chip Generator☆3,869Sep 13, 2026Updated last week
- Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2☆2,854Mar 24, 2021Updated 5 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- QEMU with RISC-V (RV64G, RV32G) Emulation Support☆388Apr 12, 2019Updated 7 years ago
- RISC-V Instruction Set Manual☆4,816Updated this week
- Source files for SiFive's Freedom platforms☆1,147Jul 17, 2026Updated 2 months ago
- RISC-V Proxy Kernel☆708Oct 2, 2025Updated 11 months ago
- ☆1,244Updated this week
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,241Sep 11, 2026Updated last week
- educational microarchitectures for risc-v isa☆754Sep 1, 2025Updated last year
- Chisel: A Modern Hardware Design Language☆4,785Sep 11, 2026Updated last week
- RISC-V Opcodes☆878Updated this week
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆367May 22, 2023Updated 3 years ago
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆3,123Updated this week
- chisel tutorial exercises and answers☆756Jan 6, 2022Updated 4 years ago
- Support for Rocket Chip on Zynq FPGAs☆424Jan 29, 2019Updated 7 years ago
- Flexible Intermediate Representation for RTL☆746Aug 20, 2024Updated 2 years ago
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,392Sep 13, 2026Updated last week
- The root repo for lowRISC project and FPGA demos.☆601Aug 3, 2023Updated 3 years ago
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,267Updated this week
- PicoRV32 - A Size-Optimized RISC-V CPU☆4,384Sep 7, 2026Updated 2 weeks ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- Generator Bootcamp Material: Learn Chisel the Right Way☆1,158Sep 10, 2024Updated 2 years ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,291Aug 26, 2026Updated 3 weeks ago
- RISC-V Frontend Server☆65Mar 31, 2019Updated 7 years ago
- FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility☆1,041Sep 10, 2026Updated last week
- Open Source Software for Developing on the Freedom E Platform - Deprecated☆584Jul 1, 2024Updated 2 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Nov 24, 2019Updated 6 years ago
- Fork of OpenOCD that has RISC-V support☆517Jul 17, 2026Updated 2 months ago
- RISC-V Assembly Programmer's Manual☆1,645Sep 4, 2026Updated 2 weeks ago
- RISC-V simulator for x86-64☆726Feb 5, 2022Updated 4 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- Working draft of the proposed RISC-V V vector extension☆1,088Mar 17, 2024Updated 2 years ago
- The Ultra-Low Power RISC-V Core☆1,920Aug 6, 2025Updated last year
- Random instruction generator for RISC-V processor verification☆1,357Sep 4, 2026Updated 2 weeks ago
- Common RTL blocks used in SiFive's projects☆194May 13, 2022Updated 4 years ago
- JavaScript RISC-V ISA Simulator. Boots linux in a web-browser.☆360Aug 25, 2020Updated 6 years ago
- Deprecated, please go to https://github.com/riscv-mcu/hbird-sdk/☆115Mar 24, 2021Updated 5 years ago
- A template project for beginning new Chisel work☆708Feb 24, 2026Updated 6 months ago