RISC-V Tools (ISA Simulator and Tests)
☆1,176Dec 22, 2022Updated 3 years ago
Alternatives and similar repositories for riscv-tools
Users that are interested in riscv-tools are comparing it to the libraries listed below
Sorting:
- GNU toolchain for RISC-V, including GCC☆4,381Feb 13, 2026Updated 2 weeks ago
- Spike, a RISC-V ISA Simulator☆3,024Updated this week
- RISC-V Linux Port☆607Apr 12, 2019Updated 6 years ago
- Rocket Chip Generator☆3,696Updated this week
- RISC-V Instruction Set Manual☆4,514Updated this week
- QEMU with RISC-V (RV64G, RV32G) Emulation Support☆388Apr 12, 2019Updated 6 years ago
- Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2☆2,814Mar 24, 2021Updated 4 years ago
- RISC-V Proxy Kernel☆687Oct 2, 2025Updated 5 months ago
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,083Feb 5, 2026Updated 3 weeks ago
- ☆1,128Jan 22, 2026Updated last month
- educational microarchitectures for risc-v isa☆740Sep 1, 2025Updated 6 months ago
- RISC-V Opcodes☆841Feb 21, 2026Updated last week
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,828Updated this week
- ☆373May 22, 2023Updated 2 years ago
- Chisel: A Modern Hardware Design Language☆4,588Updated this week
- The root repo for lowRISC project and FPGA demos.☆602Aug 3, 2023Updated 2 years ago
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,149Updated this week
- PicoRV32 - A Size-Optimized RISC-V CPU☆3,966Jun 27, 2024Updated last year
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,032Feb 11, 2026Updated 2 weeks ago
- Flexible Intermediate Representation for RTL☆748Aug 20, 2024Updated last year
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,190May 26, 2025Updated 9 months ago
- chisel tutorial exercises and answers☆747Jan 6, 2022Updated 4 years ago
- Support for Rocket Chip on Zynq FPGAs☆416Jan 29, 2019Updated 7 years ago
- Fork of OpenOCD that has RISC-V support☆510Oct 9, 2025Updated 4 months ago
- RISC-V simulator for x86-64☆722Feb 5, 2022Updated 4 years ago
- RISC-V Assembly Programmer's Manual☆1,612Updated this week
- Generator Bootcamp Material: Learn Chisel the Right Way☆1,113Sep 10, 2024Updated last year
- FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility☆997Updated this week
- Working draft of the proposed RISC-V V vector extension☆1,072Mar 17, 2024Updated last year
- RISC-V Frontend Server☆64Mar 31, 2019Updated 6 years ago
- Random instruction generator for RISC-V processor verification☆1,257Oct 1, 2025Updated 5 months ago
- RISC-V Cores, SoC platforms and SoCs☆912Mar 26, 2021Updated 4 years ago
- JavaScript RISC-V ISA Simulator. Boots linux in a web-browser.☆356Aug 25, 2020Updated 5 years ago
- VeeR EH1 core☆929May 29, 2023Updated 2 years ago
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,774Feb 17, 2026Updated last week
- A template project for beginning new Chisel work☆692Updated this week
- Working Draft of the RISC-V Debug Specification Standard☆504Feb 5, 2026Updated 3 weeks ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Nov 24, 2019Updated 6 years ago
- The Ultra-Low Power RISC-V Core☆1,738Aug 6, 2025Updated 6 months ago