RALC88 / riscv-vectorized-benchmark-suite
RiVEC Bencmark Suite
☆109Updated 2 months ago
Alternatives and similar repositories for riscv-vectorized-benchmark-suite:
Users that are interested in riscv-vectorized-benchmark-suite are comparing it to the libraries listed below
- A matrix extension proposal for AI applications under RISC-V architecture☆124Updated this week
- upstream: https://github.com/RALC88/gem5☆31Updated last year
- Unit tests generator for RVV 1.0☆74Updated last week
- ☆89Updated last year
- Modeling Architectural Platform☆176Updated 2 weeks ago
- ☆74Updated this week
- An integrated power, area, and timing modeling framework for multicore and manycore architectures☆178Updated 4 years ago
- Wrapper for Rocket-Chip on FPGAs☆129Updated 2 years ago
- The gem5-X open source framework (based on the gem5 simulator)☆38Updated last year
- A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code☆102Updated last week
- Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model☆149Updated this week
- ☆33Updated 7 months ago
- End-to-end SoC simulation: integrating the gem5 system simulator with the Aladdin accelerator simulator.☆228Updated 2 years ago
- Comment on the rocket-chip source code☆170Updated 6 years ago
- This is an read-only mirror of the gem5 simulator. The upstream repository is stored in https://gem5.googlesource.com, code reviews shoul…☆20Updated 3 years ago
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆149Updated last year
- DRAMSys a SystemC TLM-2.0 based DRAM simulator.☆241Updated 3 months ago
- This is an read-only mirror of the gem5 simulator. The upstream repository is stored in https://gem5.googlesource.com, code reviews shoul…☆11Updated 2 years ago
- Release of stream-specialization software/hardware stack.☆120Updated last year
- Repository containing the guide and code for booting RISC-V full system linux using gem5.☆48Updated 3 years ago
- ☆154Updated 3 weeks ago
- Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)☆58Updated last year
- ☆167Updated last year
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆99Updated last year
- GPGPU supporting RISCV-V, developed with verilog HDL☆83Updated 6 months ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆118Updated last week
- Tests for example Rocket Custom Coprocessors☆69Updated 4 years ago
- Benchmarks for Accelerator Design and Customized Architectures☆117Updated 4 years ago
- ☆83Updated 2 years ago
- Documentation for RISC-V Spike☆99Updated 6 years ago