RiVEC Bencmark Suite
☆132Nov 27, 2024Updated last year
Alternatives and similar repositories for riscv-vectorized-benchmark-suite
Users that are interested in riscv-vectorized-benchmark-suite are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- This is an read-only mirror of the gem5 simulator. The upstream repository is stored in https://gem5.googlesource.com, code reviews shoul…☆19Aug 21, 2021Updated 4 years ago
- A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code☆147Jan 27, 2026Updated 2 months ago
- Original test vector of RISC-V Vector Extension☆14Mar 23, 2021Updated 5 years ago
- RISC-V Zve32x, Zve32f, Zvfh Vector Coprocessor☆17Apr 8, 2026Updated last week
- Unit tests generator for RVV 1.0☆106Nov 11, 2025Updated 5 months ago
- Serverless GPU API endpoints on Runpod - Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- ☆370Updated this week
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆505Updated this week
- ☆12Feb 15, 2024Updated 2 years ago
- Vector processor for RISC-V vector ISA☆139Oct 19, 2020Updated 5 years ago
- Fork of gem5 with support for manycore architectures. Includes models and scripts to evaluate a software-defined-vector architecture.☆12Oct 14, 2021Updated 4 years ago
- A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code. (Results)☆47Jan 31, 2026Updated 2 months ago
- ☆15Jan 11, 2023Updated 3 years ago
- Implements kernels with RISC-V Vector☆22Mar 24, 2023Updated 3 years ago
- upstream: https://github.com/RALC88/gem5☆33May 30, 2023Updated 2 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- Chisel RISC-V Vector 1.0 Implementation☆143Updated this week
- PLCT实验室的 RISC-V V Spec 实现，基于llvm/llvm-project，rkruppe/rvv-llvm 和 https://repo.hca.bsc.es/gitlab/rferrer/llvm-epi-0.8☆160Sep 3, 2025Updated 7 months ago
- Working draft of the proposed RISC-V V vector extension☆1,076Mar 17, 2024Updated 2 years ago
- PLCT实验室 rvv-llvm 实现配套的 benchmark / testcases☆21Nov 26, 2020Updated 5 years ago
- RISC-V vector extension ISA simulation☆18Jun 11, 2019Updated 6 years ago
- This is a repo for recording and reporting RISCV platform's test and measurement continuously.☆60Dec 19, 2023Updated 2 years ago
- A translator from ARM NEON intrinsics to RISCV-V Extension implementation☆43Updated this week
- ☆200Dec 14, 2023Updated 2 years ago
- Championship Value Prediction (CVP) simulator.☆17Feb 17, 2021Updated 5 years ago
- Serverless GPU API endpoints on Runpod - Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- RISC-V Vectorized Bencmark Suite. based on https://github.com/RALC88/riscv-vectorized-benchmark-suite☆12Oct 28, 2022Updated 3 years ago
- ☆11Jan 9, 2021Updated 5 years ago
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆166Jan 25, 2024Updated 2 years ago
- RISC-V vector and other assembly code examples☆28Nov 4, 2020Updated 5 years ago
- ☆64Dec 4, 2022Updated 3 years ago
- ☆14Apr 1, 2026Updated 2 weeks ago
- Unlimited Vector Extension with Data Streaming Support☆12Nov 25, 2024Updated last year
- SystemC training aimed at TLM.☆35Jul 31, 2020Updated 5 years ago
- Updated C version of the Test Suite for Vectorising Compilers☆73Mar 14, 2024Updated 2 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Nuclei AI Library Optimized For RISC-V Vector☆15Oct 15, 2025Updated 6 months ago
- A translator from Intel SSE intrinsics to RISCV-V Extension implementation☆26Updated this week
- Run Rocket Chip on VCU128☆30Oct 21, 2025Updated 5 months ago
- The University of Bristol HPC Simulation Engine☆109Aug 30, 2025Updated 7 months ago
- GPGPU processor supporting RISCV-V extension, developed with Chisel HDL☆886Updated this week
- NeuroVectorizer is a framework that uses deep reinforcement learning (RL) to predict optimal vectorization compiler pragmas for for loops…☆99Jan 7, 2023Updated 3 years ago
- This project records the process of optimizing SGEMM (single-precision floating point General Matrix Multiplication) on the riscv platfor…☆24Dec 11, 2024Updated last year