RiVEC Bencmark Suite
☆128Nov 27, 2024Updated last year
Alternatives and similar repositories for riscv-vectorized-benchmark-suite
Users that are interested in riscv-vectorized-benchmark-suite are comparing it to the libraries listed below
Sorting:
- A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code☆145Jan 27, 2026Updated last month
- This is an read-only mirror of the gem5 simulator. The upstream repository is stored in https://gem5.googlesource.com, code reviews shoul…☆19Aug 21, 2021Updated 4 years ago
- Original test vector of RISC-V Vector Extension☆14Mar 23, 2021Updated 4 years ago
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆495Nov 27, 2025Updated 3 months ago
- ☆12Feb 15, 2024Updated 2 years ago
- ☆364Feb 24, 2026Updated last week
- RISC-V Zve32x, Zve32f, Zvfh Vector Coprocessor☆16Feb 17, 2026Updated 2 weeks ago
- Unit tests generator for RVV 1.0☆103Nov 11, 2025Updated 3 months ago
- A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code. (Results)☆47Jan 31, 2026Updated last month
- Vector processor for RISC-V vector ISA☆137Oct 19, 2020Updated 5 years ago
- PLCT实验室 rvv-llvm 实现配套的 benchmark / testcases☆21Nov 26, 2020Updated 5 years ago
- Implements kernels with RISC-V Vector☆22Mar 24, 2023Updated 2 years ago
- Chisel RISC-V Vector 1.0 Implementation☆136Feb 25, 2026Updated last week
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆162Jan 25, 2024Updated 2 years ago
- RISC-V vector extension ISA simulation☆16Jun 11, 2019Updated 6 years ago
- PLCT实验室的 RISC-V V Spec 实现,基于llvm/llvm-project,rkruppe/rvv-llvm 和 https://repo.hca.bsc.es/gitlab/rferrer/llvm-epi-0.8☆160Sep 3, 2025Updated 6 months ago
- ☆43Mar 31, 2025Updated 11 months ago
- RISC-V Zve32x Vector Coprocessor☆207Jan 22, 2026Updated last month
- Basic floating-point components for RISC-V processors☆67Dec 4, 2019Updated 6 years ago
- Championship Value Prediction (CVP) simulator.☆17Feb 17, 2021Updated 5 years ago
- ☆11Jan 9, 2021Updated 5 years ago
- GPGPU processor supporting RISCV-V extension, developed with Chisel HDL☆875Updated this week
- Run Rocket Chip on VCU128☆30Oct 21, 2025Updated 4 months ago
- Working draft of the proposed RISC-V V vector extension☆1,072Mar 17, 2024Updated last year
- Updated C version of the Test Suite for Vectorising Compilers☆71Mar 14, 2024Updated last year
- Generic AHB master stub☆12Jul 17, 2014Updated 11 years ago
- RISC-V Virtual Prototype☆46Oct 1, 2021Updated 4 years ago
- Nuclei AI Library Optimized For RISC-V Vector☆14Oct 15, 2025Updated 4 months ago
- muRISCV-NN is a collection of efficient deep learning kernels for embedded platforms and microcontrollers.☆94Oct 6, 2025Updated 5 months ago
- A matrix extension proposal for AI applications under RISC-V architecture☆164Feb 11, 2025Updated last year
- ☆196Dec 14, 2023Updated 2 years ago
- This project records the process of optimizing SGEMM (single-precision floating point General Matrix Multiplication) on the riscv platfor…☆24Dec 11, 2024Updated last year
- A translator from ARM NEON intrinsics to RISCV-V Extension implementation☆41Aug 25, 2025Updated 6 months ago
- RISC-V Vectorized Bencmark Suite. based on https://github.com/RALC88/riscv-vectorized-benchmark-suite☆12Oct 28, 2022Updated 3 years ago
- ☆18May 13, 2025Updated 9 months ago
- Fork of gem5 with support for manycore architectures. Includes models and scripts to evaluate a software-defined-vector architecture.☆12Oct 14, 2021Updated 4 years ago
- Simple demonstration of using the RISC-V Vector extension☆50Apr 18, 2024Updated last year
- matrix-coprocessor for RISC-V☆30Feb 27, 2026Updated last week
- SystemC training aimed at TLM.☆35Jul 31, 2020Updated 5 years ago