Alternatives and similar repositories for riscv-gcc

Users that are interested in riscv-gcc are comparing it to the libraries listed below

• riscv-software-src / riscv-pk
  RISC-V Proxy Kernel
  ☆636Updated last month
• riscv / riscv-debug-spec
  Working Draft of the RISC-V Debug Specification Standard
  ☆490Updated 3 weeks ago
• riscvarchive / riscv-software-list
  The RISC-V software tools list, as seen on riscv.org
  ☆465Updated 4 years ago
• riscv-collab / riscv-openocd
  Fork of OpenOCD that has RISC-V support
  ☆483Updated last month
• riscv-software-src / riscv-tools
  RISC-V Tools (ISA Simulator and Tests)
  ☆1,170Updated 2 years ago
• riscv-non-isa / riscv-arch-test
  ☆564Updated 2 weeks ago
• riscvarchive / riscv-binutils-gdb
  RISC-V backports for binutils-gdb. Development is done upstream at the FSF.
  ☆149Updated 2 years ago
• riscv / riscv-opcodes
  RISC-V Opcodes
  ☆766Updated 3 weeks ago
• riscv-software-src / riscv-tests
  ☆1,011Updated last month
• ucb-bar / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆714Updated 2 months ago
• ucb-bar / riscv-mini
  Simple RISC-V 3-stage Pipeline in Chisel
  ☆578Updated 9 months ago
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,077Updated this week
• riscvarchive / riscv-cores-list
  RISC-V Cores, SoC platforms and SoCs
  ☆881Updated 4 years ago
• riscv / riscv-fast-interrupt
  Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
  ☆268Updated this week
• SymbioticEDA / riscv-formal
  RISC-V Formal Verification Framework
  ☆602Updated 3 years ago
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆878Updated 2 years ago
• riscvarchive / riscv-qemu
  QEMU with RISC-V (RV64G, RV32G) Emulation Support
  ☆391Updated 6 years ago
• riscv / riscv-bitmanip
  Working draft of the proposed RISC-V Bitmanipulation extension
  ☆211Updated last year
• riscvarchive / risc-v-getting-started-guide
  The official RISC-V getting started guide
  ☆200Updated last year
• XUANTIE-RV / openc906
  OpenXuantie - OpenC906 Core
  ☆354Updated 11 months ago
• RoaLogic / RV12
  RISC-V CPU Core
  ☆325Updated 11 months ago
• riscv-non-isa / riscv-trace-spec
  RISC-V Processor Trace Specification
  ☆182Updated 2 weeks ago
• riscv-non-isa / riscv-sbi-doc
  Documentation for the RISC-V Supervisor Binary Interface
  ☆405Updated 3 weeks ago
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆667Updated 6 months ago
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆706Updated last week
• sifiveinc / freedom-u-sdk
  Freedom U Software Development Kit (FUSDK)
  ☆289Updated last week
• openrisc / mor1kx
  mor1kx - an OpenRISC 1000 processor IP core
  ☆535Updated 2 months ago
• bluespec / Flute
  RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance
  ☆368Updated last year
• chipsalliance / firrtl
  Flexible Intermediate Representation for RTL
  ☆741Updated 9 months ago
• syntacore / scr1
  SCR1 is a high-quality open-source RISC-V MCU core in Verilog
  ☆914Updated 6 months ago