ucb-bar / hwacha
Microarchitecture implementation of the decoupled vector-fetch accelerator
☆146Updated 7 months ago
Related projects: ⓘ
- A Chisel RTL generator for network-on-chip interconnects☆162Updated 3 weeks ago
- ☆71Updated 2 years ago
- A Library of Chisel3 Tools for Digital Signal Processing☆221Updated 4 months ago
- Vector Acceleration IP core for RISC-V*☆130Updated this week
- A Style Guide for the Chisel Hardware Construction Language☆106Updated 3 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆93Updated last year
- Wrapper for Rocket-Chip on FPGAs☆120Updated last year
- The batteries-included testing and formal verification library for Chisel-based RTL designs.☆220Updated last month
- A dynamic verification library for Chisel.☆138Updated 3 months ago
- Chisel implementation of the NVIDIA Deep Learning Accelerator (NVDLA), with self-driving accelerated☆219Updated last week
- ☆76Updated 6 months ago
- Chisel components for FPGA projects☆114Updated last year
- Tests for example Rocket Custom Coprocessors☆68Updated 4 years ago
- RISC-V Torture Test☆163Updated 2 months ago
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆169Updated 4 years ago
- CVA6 SDK containing RISC-V tools and Buildroot☆59Updated 2 months ago
- ☆285Updated last week
- ☆80Updated 3 weeks ago
- RiVEC Bencmark Suite☆88Updated 3 weeks ago
- Tile based architecture designed for computing efficiency, scalability and generality☆225Updated this week
- Chisel/Firrtl execution engine☆152Updated 3 weeks ago
- RiscyOO: RISC-V Out-of-Order Processor☆148Updated 4 years ago
- Provides dot visualizations of chisel/firrtl circuits☆114Updated last year
- Provides various testers for chisel users☆98Updated last year
- Comment on the rocket-chip source code☆167Updated 5 years ago
- A matrix extension proposal for AI applications under RISC-V architecture☆93Updated 2 months ago
- Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel☆206Updated 4 years ago
- Advanced Interface Bus (AIB) die-to-die hardware open source☆118Updated 6 months ago
- Chisel Learning Journey☆105Updated last year
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆161Updated last month