chipsalliance / riscv-vector-testsLinks
Unit tests generator for RVV 1.0
☆100Updated 3 months ago
Alternatives and similar repositories for riscv-vector-tests
Users that are interested in riscv-vector-tests are comparing it to the libraries listed below
Sorting:
- Chisel RISC-V Vector 1.0 Implementation☆131Updated 4 months ago
- RiVEC Bencmark Suite☆127Updated last year
- A matrix extension proposal for AI applications under RISC-V architecture☆162Updated last year
- Modeling Architectural Platform☆219Updated this week
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆136Updated this week
- Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model☆209Updated this week
- Vector processor for RISC-V vector ISA☆136Updated 5 years ago
- Advanced Architecture Labs with CVA6☆77Updated 2 years ago
- A Chisel RTL generator for network-on-chip interconnects☆226Updated 3 months ago
- ☆125Updated this week
- An energy-efficient RISC-V floating-point compute cluster.☆123Updated 3 weeks ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆98Updated this week
- CVA6 SDK containing RISC-V tools and Buildroot☆78Updated 2 weeks ago
- ☆193Updated 2 years ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆195Updated this week
- RISC-V Torture Test☆213Updated last year
- A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code☆143Updated 2 weeks ago
- A Fast, Low-Overhead On-chip Network☆267Updated 2 weeks ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆73Updated last year
- RISC-V IOMMU Specification☆146Updated this week
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆114Updated 2 years ago
- A Style Guide for the Chisel Hardware Construction Language☆109Updated 4 years ago
- IOMMU IP compliant with the RISC-V IOMMU Specification v1.0☆111Updated 4 months ago
- Instruction Set Generator initially contributed by Futurewei☆306Updated 2 years ago
- RISC-V Packed SIMD Extension☆157Updated this week
- Open source high performance IEEE-754 floating unit☆89Updated last year
- high-performance RTL simulator☆186Updated last year
- A dynamic verification library for Chisel.☆160Updated last year
- ☆89Updated 5 months ago
- RISC-V Vector (RVV) Automatic Tests Generator with full instructions coverage, including self-checking test and signature test (RISC-V Co…☆16Updated last year