chipsalliance / riscv-vector-testsLinks
Unit tests generator for RVV 1.0
☆100Updated 3 months ago
Alternatives and similar repositories for riscv-vector-tests
Users that are interested in riscv-vector-tests are comparing it to the libraries listed below
Sorting:
- Chisel RISC-V Vector 1.0 Implementation☆131Updated 4 months ago
- RiVEC Bencmark Suite☆127Updated last year
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆136Updated this week
- A matrix extension proposal for AI applications under RISC-V architecture☆161Updated last year
- Modeling Architectural Platform☆219Updated this week
- Vector processor for RISC-V vector ISA☆136Updated 5 years ago
- Advanced Architecture Labs with CVA6☆77Updated 2 years ago
- Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model☆209Updated this week
- A Chisel RTL generator for network-on-chip interconnects☆226Updated 3 months ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆98Updated this week
- A Fast, Low-Overhead On-chip Network☆267Updated 2 weeks ago
- ☆193Updated 2 years ago
- ☆125Updated this week
- RISC-V Torture Test☆213Updated last year
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆195Updated this week
- An energy-efficient RISC-V floating-point compute cluster.☆123Updated 3 weeks ago
- Open source high performance IEEE-754 floating unit☆89Updated last year
- Top project for RISC-V Matrix extension proposal and related opensource implementations.☆35Updated last year
- A Style Guide for the Chisel Hardware Construction Language☆109Updated 4 years ago
- An open-source UCIe implementation☆82Updated 2 weeks ago
- CVA6 SDK containing RISC-V tools and Buildroot☆78Updated 2 weeks ago
- Modern co-simulation framework for RISC-V CPUs☆171Updated last week
- high-performance RTL simulator☆186Updated last year
- Pick your favorite language to verify your chip.☆77Updated last week
- eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V☆239Updated this week
- Setup scripts and files needed to compile CoreMark on RISC-V☆73Updated last year
- Tests for example Rocket Custom Coprocessors☆75Updated 5 years ago
- RISC-V Vector (RVV) Automatic Tests Generator with full instructions coverage, including self-checking test and signature test (RISC-V Co…☆16Updated last year
- upstream: https://github.com/RALC88/gem5☆33Updated 2 years ago
- Wrapper for Rocket-Chip on FPGAs☆137Updated 3 years ago