Unit tests generator for RVV 1.0
☆103Nov 11, 2025Updated 3 months ago
Alternatives and similar repositories for riscv-vector-tests
Users that are interested in riscv-vector-tests are comparing it to the libraries listed below
Sorting:
- A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code☆145Jan 27, 2026Updated last month
- Original test vector of RISC-V Vector Extension☆14Mar 23, 2021Updated 4 years ago
- RISC-V Vector (RVV) Automatic Tests Generator with full instructions coverage, including self-checking test and signature test (RISC-V Co…☆16Apr 3, 2024Updated last year
- Generate Linux Perf event tables for Apple Silicon☆17Dec 16, 2025Updated 2 months ago
- Minimal RISC-V Chisel design strictly reflecting the ISA document for verification.☆18Feb 3, 2026Updated last month
- Chisel RISC-V Vector 1.0 Implementation☆133Feb 25, 2026Updated last week
- A translator from ARM NEON intrinsics to RISCV-V Extension implementation☆41Aug 25, 2025Updated 6 months ago
- Dump Apple PMU counter definitions from `/usr/share/kpep` in macOS☆16Jan 8, 2026Updated last month
- ☆311Feb 6, 2026Updated 3 weeks ago
- Simple demonstration of using the RISC-V Vector extension☆50Apr 18, 2024Updated last year
- RiVEC Bencmark Suite☆127Nov 27, 2024Updated last year
- RISC-V模拟器，相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册☆54Apr 11, 2020Updated 5 years ago
- A Rocket-based RISC-V superscalar in-order core☆38Feb 24, 2026Updated last week
- Fuzzing General-Purpose Hardware Designs with Software Fuzzers☆24Jan 11, 2026Updated last month
- A riscv emulator.☆19Feb 5, 2024Updated 2 years ago
- RISC-V Zve32x, Zve32f, Zvfh Vector Coprocessor☆16Feb 17, 2026Updated 2 weeks ago
- RISC-V Architecture Profiles☆175Feb 18, 2026Updated 2 weeks ago
- Sail RISC-V model☆671Updated this week
- Vector processor for RISC-V vector ISA☆137Oct 19, 2020Updated 5 years ago
- A matrix extension proposal for AI applications under RISC-V architecture☆164Feb 11, 2025Updated last year
- Instruction Set Generator initially contributed by Futurewei☆306Oct 17, 2023Updated 2 years ago
- Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit☆38Dec 23, 2021Updated 4 years ago
- PLCT实验室 rvv-llvm 实现配套的 benchmark / testcases☆21Nov 26, 2020Updated 5 years ago
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆495Nov 27, 2025Updated 3 months ago
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆34Updated this week
- ☆364Feb 24, 2026Updated last week
- Paging Debug tool for GDB using python☆13Jun 4, 2022Updated 3 years ago
- RISC-V architecture concurrency model litmus tests☆100Jan 21, 2026Updated last month
- ☆23Mar 15, 2023Updated 2 years ago
- A translator from Intel SSE intrinsics to RISCV-V Extension implementation☆24Aug 25, 2025Updated 6 months ago
- ☆15Sep 27, 2022Updated 3 years ago
- Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boards☆20Nov 27, 2024Updated last year
- A collection of tests and benchmarks for the Arc simulation backend of CIRCT☆36Jan 26, 2026Updated last month
- The Next-gen Language & Compiler Powering Efficient Hardware Design☆36Jan 16, 2025Updated last year
- This repo includes XiangShan's function units☆30Feb 14, 2026Updated 2 weeks ago
- Implementing the Precise Runahead (HPCA'20) in gem5☆13Oct 5, 2023Updated 2 years ago
- ☆17Mar 26, 2025Updated 11 months ago
- 给NEMU移植Linux Kernel!☆22Jun 1, 2025Updated 9 months ago
- GPGPU processor supporting RISCV-V extension, developed with Chisel HDL☆871Jan 31, 2026Updated last month