Unit tests generator for RVV 1.0
☆113May 25, 2026Updated 2 weeks ago
Alternatives and similar repositories for riscv-vector-tests
Users that are interested in riscv-vector-tests are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Original test vector of RISC-V Vector Extension☆14Mar 23, 2021Updated 5 years ago
- RISC-V Vector (RVV) Automatic Tests Generator with full instructions coverage, including self-checking test and signature test (RISC-V Co…☆17Apr 3, 2024Updated 2 years ago
- A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code☆151Apr 19, 2026Updated last month
- Simple demonstration of using the RISC-V Vector extension☆51Apr 18, 2024Updated 2 years ago
- ☆318May 13, 2026Updated last month
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- RISC-V模拟器,相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册☆54Apr 11, 2020Updated 6 years ago
- RiVEC Bencmark Suite☆132Nov 27, 2024Updated last year
- A translator from ARM NEON intrinsics to RISCV-V Extension implementation☆44Apr 25, 2026Updated last month
- A Rocket-based RISC-V superscalar in-order core☆40Mar 11, 2026Updated 3 months ago
- ☆15Sep 27, 2022Updated 3 years ago
- Vector processor for RISC-V vector ISA☆138Oct 19, 2020Updated 5 years ago
- Generate Linux Perf event tables for Apple Silicon☆17Dec 16, 2025Updated 5 months ago
- Instruction Set Generator initially contributed by Futurewei☆307Oct 17, 2023Updated 2 years ago
- ☆376Jun 5, 2026Updated last week
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- Chisel RISC-V Vector 1.0 Implementation☆147Apr 23, 2026Updated last month
- A translator from Intel SSE intrinsics to RISCV-V Extension implementation☆27Apr 11, 2026Updated 2 months ago
- PLCT实验室 rvv-llvm 实现配套的 benchmark / testcases☆21Nov 26, 2020Updated 5 years ago
- Sail RISC-V model☆719Updated this week
- A matrix extension proposal for AI applications under RISC-V architecture☆183Apr 1, 2026Updated 2 months ago
- Minimal RISC-V Chisel design strictly reflecting the ISA document for verification.☆20Apr 14, 2026Updated 2 months ago
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆524Updated this week
- This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usag…☆23Mar 10, 2026Updated 3 months ago
- A riscv emulator.☆19Feb 5, 2024Updated 2 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Fuzzing General-Purpose Hardware Designs with Software Fuzzers☆27Mar 8, 2026Updated 3 months ago
- Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit☆39Dec 23, 2021Updated 4 years ago
- Ocelot: The Berkeley Out-of-Order Machine With V-EXT support☆253May 29, 2026Updated 2 weeks ago
- RISC-V Architecture Profiles☆188Apr 22, 2026Updated last month
- RISC-V Zve32x, Zve32f, Zvfh Vector Coprocessor☆19Apr 8, 2026Updated 2 months ago
- ☆29Apr 21, 2026Updated last month
- RADIX-4 SRT division☆12Oct 31, 2019Updated 6 years ago
- GPGPU processor supporting RISCV-V extension, developed with Chisel HDL☆915Updated this week
- RISC-V Torture Test☆216Jul 11, 2024Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Vector math library using RISC-V vector ISA via C intrinsic☆25Mar 27, 2026Updated 2 months ago
- Top project for RISC-V Matrix extension proposal and related opensource implementations.☆38Mar 26, 2024Updated 2 years ago
- Dump Apple PMU counter definitions from `/usr/share/kpep` in macOS☆16Mar 25, 2026Updated 2 months ago
- ☆23Mar 15, 2023Updated 3 years ago
- Working draft of the proposed RISC-V V vector extension☆1,083Mar 17, 2024Updated 2 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆133Jul 11, 2025Updated 11 months ago
- This repo includes XiangShan's function units☆30Jun 3, 2026Updated last week