chipsalliance / riscv-vector-testsLinks
Unit tests generator for RVV 1.0
☆85Updated 3 weeks ago
Alternatives and similar repositories for riscv-vector-tests
Users that are interested in riscv-vector-tests are comparing it to the libraries listed below
Sorting:
- Chisel RISC-V Vector 1.0 Implementation☆98Updated 3 weeks ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆110Updated last week
- A matrix extension proposal for AI applications under RISC-V architecture☆148Updated 3 months ago
- Vector processor for RISC-V vector ISA☆119Updated 4 years ago
- RiVEC Bencmark Suite☆116Updated 6 months ago
- RISC-V Vector (RVV) Automatic Tests Generator with full instructions coverage, including self-checking test and signature test (RISC-V Co…☆15Updated last year
- A Fast, Low-Overhead On-chip Network☆207Updated this week
- ☆175Updated last year
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆77Updated this week
- A dynamic verification library for Chisel.☆151Updated 6 months ago
- Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model☆176Updated this week
- Vector Acceleration IP core for RISC-V*☆178Updated 3 weeks ago
- Wrapper for Rocket-Chip on FPGAs☆134Updated 2 years ago
- A Chisel RTL generator for network-on-chip interconnects☆198Updated 3 weeks ago
- Top project for RISC-V Matrix extension proposal and related opensource implementations.☆30Updated last year
- Modeling Architectural Platform☆190Updated this week
- Advanced Architecture Labs with CVA6☆61Updated last year
- RISC-V Matrix Specification☆22Updated 6 months ago
- ☆86Updated this week
- Setup scripts and files needed to compile CoreMark on RISC-V☆68Updated 10 months ago
- An energy-efficient RISC-V floating-point compute cluster.☆84Updated this week
- GPGPU supporting RISCV-V, developed with verilog HDL☆101Updated 3 months ago
- Tests for example Rocket Custom Coprocessors☆74Updated 5 years ago
- ☆135Updated last year
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆160Updated this week
- CVA6 SDK containing RISC-V tools and Buildroot☆66Updated 11 months ago
- RISC-V architecture concurrency model litmus tests☆78Updated last week
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆105Updated last year
- IOMMU IP compliant with the RISC-V IOMMU Specification v1.0☆94Updated 2 months ago
- RISC-V Torture Test☆195Updated 10 months ago