chipsalliance / riscv-vector-tests
Unit tests generator for RVV 1.0
☆82Updated 3 weeks ago
Alternatives and similar repositories for riscv-vector-tests:
Users that are interested in riscv-vector-tests are comparing it to the libraries listed below
- A matrix extension proposal for AI applications under RISC-V architecture☆138Updated 2 months ago
- Chisel RISC-V Vector 1.0 Implementation☆93Updated last week
- RiVEC Bencmark Suite☆114Updated 4 months ago
- Vector Acceleration IP core for RISC-V*☆175Updated last week
- A dynamic verification library for Chisel.☆148Updated 5 months ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆105Updated this week
- Vector processor for RISC-V vector ISA☆117Updated 4 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆71Updated last week
- Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model☆163Updated last week
- A Fast, Low-Overhead On-chip Network☆195Updated 2 weeks ago
- RISC-V Vector (RVV) Automatic Tests Generator with full instructions coverage, including self-checking test and signature test (RISC-V Co…☆14Updated last year
- GPGPU supporting RISCV-V, developed with verilog HDL☆92Updated 2 months ago
- A Chisel RTL generator for network-on-chip interconnects☆194Updated last month
- ☆80Updated this week
- Modeling Architectural Platform☆185Updated this week
- Open source high performance IEEE-754 floating unit☆70Updated last year
- Setup scripts and files needed to compile CoreMark on RISC-V☆65Updated 9 months ago
- Top project for RISC-V Matrix extension proposal and related opensource implementations.☆30Updated last year
- IOMMU IP compliant with the RISC-V IOMMU Specification v1.0☆91Updated 3 weeks ago
- Advanced Architecture Labs with CVA6☆57Updated last year
- ☆92Updated last year
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆145Updated last month
- Tests for example Rocket Custom Coprocessors☆73Updated 5 years ago
- Pure digital components of a UCIe controller☆61Updated 2 weeks ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆101Updated last year
- RISC-V Verification Interface☆89Updated 2 months ago
- A Style Guide for the Chisel Hardware Construction Language☆107Updated 3 years ago
- RISC-V Matrix Specification☆21Updated 4 months ago
- high-performance RTL simulator☆156Updated 10 months ago
- RISC-V Torture Test☆190Updated 9 months ago