chipsalliance / riscv-vector-tests
Unit tests generator for RVV 1.0
☆62Updated last month
Related projects ⓘ
Alternatives and complementary repositories for riscv-vector-tests
- Chisel RISC-V Vector 1.0 Implementation☆54Updated this week
- A matrix extension proposal for AI applications under RISC-V architecture☆109Updated 3 weeks ago
- RiVEC Bencmark Suite☆105Updated 2 weeks ago
- Tests for example Rocket Custom Coprocessors☆69Updated 4 years ago
- Advanced Architecture Labs with CVA6☆49Updated 10 months ago
- RISC-V Vector (RVV) Automatic Tests Generator with full instructions coverage, including self-checking test and signature test (RISC-V Co…☆14Updated 7 months ago
- Vector processor for RISC-V vector ISA☆110Updated 4 years ago
- A Style Guide for the Chisel Hardware Construction Language☆106Updated 3 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆59Updated this week
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆75Updated this week
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆93Updated this week
- ☆62Updated 3 months ago
- Top project for RISC-V Matrix extension proposal and related opensource implementations.☆23Updated 7 months ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆64Updated 4 months ago
- RISC-V Matrix Specification☆15Updated 2 months ago
- Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model☆136Updated this week
- ☆75Updated 2 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆95Updated last year
- upstream: https://github.com/RALC88/gem5☆32Updated last year
- A Chisel RTL generator for network-on-chip interconnects☆177Updated this week
- Pure digital components of a UCIe controller☆48Updated 2 weeks ago
- A Fast, Low-Overhead On-chip Network☆137Updated 3 weeks ago
- Open source high performance IEEE-754 floating unit☆60Updated 8 months ago
- IOMMU IP compliant with the RISC-V IOMMU Specification v1.0☆80Updated 2 weeks ago
- CVA6 SDK containing RISC-V tools and Buildroot☆62Updated 4 months ago
- Chisel Learning Journey☆107Updated last year
- Basic floating-point components for RISC-V processors☆64Updated 4 years ago
- A dynamic verification library for Chisel.☆142Updated last week
- Vector Acceleration IP core for RISC-V*☆150Updated this week
- ☆30Updated 4 months ago