Alternatives and similar repositories for sail-riscv

Users that are interested in sail-riscv are comparing it to the libraries listed below

• rems-project / sail

  View on GitHub
  Sail architecture definition language
  ☆841Feb 6, 2026Updated last week
• riscv-non-isa / riscv-arch-test

  View on GitHub
  ☆650Updated this week
• SymbioticEDA / riscv-formal

  View on GitHub
  RISC-V Formal Verification Framework
  ☆624Apr 6, 2022Updated 3 years ago
• riscv-software-src / riscv-isa-sim

  View on GitHub
  Spike, a RISC-V ISA Simulator
  ☆3,017Feb 4, 2026Updated last week
• CTSRD-CHERI / sail-cheri-riscv

  View on GitHub
  CHERI-RISC-V model written in Sail
  ☆66Jul 10, 2025Updated 7 months ago
• riscv / riscv-opcodes

  View on GitHub
  RISC-V Opcodes
  ☆833Jan 29, 2026Updated 2 weeks ago
• CTSRD-CHERI / TestRIG

  View on GitHub
  Testing processors with Random Instruction Generation
  ☆55Jan 13, 2026Updated last month
• riscv / riscv-debug-spec

  View on GitHub
  Working Draft of the RISC-V Debug Specification Standard
  ☆504Feb 5, 2026Updated last week
• rems-project / sail-arm

  View on GitHub
  Sail version of Arm ISA definition, currently for Armv9.3-A, and with the previous Sail Armv8.5-A model
  ☆92Jan 7, 2026Updated last month
• riscv / riscv-profiles

  View on GitHub
  RISC-V Architecture Profiles
  ☆173Updated this week
• riscv-ovpsim / imperas-riscv-tests

  View on GitHub
  ☆194Dec 14, 2023Updated 2 years ago
• YosysHQ / riscv-formal

  View on GitHub
  RISC-V Formal Verification Framework
  ☆178Jan 19, 2026Updated 3 weeks ago
• riscv-software-src / riscv-tests

  View on GitHub
  ☆1,119Jan 22, 2026Updated 3 weeks ago
• chipsalliance / riscv-dv

  View on GitHub
  Random instruction generator for RISC-V processor verification
  ☆1,252Oct 1, 2025Updated 4 months ago
• openhwgroup / force-riscv

  View on GitHub
  Instruction Set Generator initially contributed by Futurewei
  ☆306Oct 17, 2023Updated 2 years ago
• riscvarchive / riscv-CMOs

  View on GitHub
  ☆89Aug 26, 2025Updated 5 months ago
• riscv / riscv-crypto

  View on GitHub
  RISC-V cryptography extensions standardisation work.
  ☆403Mar 8, 2024Updated last year
• riscv-software-src / riscv-pk

  View on GitHub
  RISC-V Proxy Kernel
  ☆687Oct 2, 2025Updated 4 months ago
• chipsalliance / dromajo

  View on GitHub
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆238Nov 20, 2024Updated last year
• riscv-non-isa / riscv-trace-spec

  View on GitHub
  RISC-V Processor Trace Specification
  ☆207Updated this week
• mit-plv / kami

  View on GitHub
  A Platform for High-Level Parametric Hardware Specification and its Modular Verification
  ☆164Nov 20, 2025Updated 2 months ago
• openhwgroup / core-v-verif

  View on GitHub
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆656Updated this week
• openhwgroup / cva6

  View on GitHub
  The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…
  ☆2,797Updated this week
• riscvarchive / riscv-code-size-reduction

  View on GitHub
  ☆148Feb 29, 2024Updated last year
• riscv / riscv-bitmanip

  View on GitHub
  Working draft of the proposed RISC-V Bitmanipulation extension
  ☆216Mar 20, 2024Updated last year
• chipsalliance / riscv-vector-tests

  View on GitHub
  Unit tests generator for RVV 1.0
  ☆102Nov 11, 2025Updated 3 months ago
• riscv-boom / riscv-boom

  View on GitHub
  SonicBOOM: The Berkeley Out-of-Order Machine
  ☆2,072Feb 5, 2026Updated last week
• ucb-bar / riscv-mini

  View on GitHub
  Simple RISC-V 3-stage Pipeline in Chisel
  ☆603Aug 9, 2024Updated last year
• lowRISC / ibex

  View on GitHub
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,764Feb 7, 2026Updated last week
• riscv / riscv-plic-spec

  View on GitHub
  PLIC Specification
  ☆150Feb 6, 2026Updated last week
• olofk / serv

  View on GitHub
  SERV - The SErial RISC-V CPU
  ☆1,751Updated this week
• riscv / riscv-fast-interrupt

  View on GitHub
  Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
  ☆286Updated this week
• rems-project / isla

  View on GitHub
  Symbolic execution tool for Sail ISA specifications
  ☆87Jan 26, 2026Updated 2 weeks ago
• riscv / riscv-isa-manual

  View on GitHub
  RISC-V Instruction Set Manual
  ☆4,488Feb 8, 2026Updated last week
• ucb-bar / riscv-torture

  View on GitHub
  RISC-V Torture Test
  ☆213Jul 11, 2024Updated last year
• chipsalliance / firrtl

  View on GitHub
  Flexible Intermediate Representation for RTL
  ☆747Aug 20, 2024Updated last year
• xinpian-tech / zaozi

  View on GitHub
  A eDSL framework based on Scala and MLIR, focusing on the Hardware design.
  ☆65Feb 4, 2026Updated last week
• rsd-devel / rsd

  View on GitHub
  RSD: RISC-V Out-of-Order Superscalar Processor
  ☆1,149Dec 25, 2025Updated last month
• riscv-software-src / riscv-config

  View on GitHub
  RISC-V Configuration Validator
  ☆81Mar 28, 2025Updated 10 months ago