Alternatives and similar repositories for sail-riscv

Users that are interested in sail-riscv are comparing it to the libraries listed below

• SymbioticEDA / riscv-formal
  RISC-V Formal Verification Framework
  ☆622Updated 3 years ago
• rems-project / sail
  Sail architecture definition language
  ☆832Updated this week
• riscv-non-isa / riscv-arch-test
  ☆638Updated this week
• riscv / riscv-bitmanip
  Working draft of the proposed RISC-V Bitmanipulation extension
  ☆216Updated last year
• riscv / riscv-opcodes
  RISC-V Opcodes
  ☆830Updated 2 weeks ago
• riscv / riscv-debug-spec
  Working Draft of the RISC-V Debug Specification Standard
  ☆504Updated 3 weeks ago
• riscv / riscv-crypto
  RISC-V cryptography extensions standardisation work.
  ☆402Updated last year
• riscv-software-src / riscv-tests
  ☆1,110Updated this week
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆304Updated 2 years ago
• riscv-software-src / riscv-pk
  RISC-V Proxy Kernel
  ☆683Updated 3 months ago
• YosysHQ / sby
  SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
  ☆486Updated this week
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆211Updated last year
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆758Updated last week
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆761Updated 4 months ago
• ucb-bar / riscv-mini
  Simple RISC-V 3-stage Pipeline in Chisel
  ☆603Updated last year
• shioyadan / Konata
  Konata is an instruction pipeline visualizer for Onikiri2-Kanata/Gem5-O3PipeView formats. You can download the pre-built binaries from ht…
  ☆509Updated last year
• bluespec / Flute
  RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance
  ☆376Updated 2 years ago
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆176Updated last week
• riscv / riscv-fast-interrupt
  Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
  ☆283Updated last week
• riscv-non-isa / riscv-trace-spec
  RISC-V Processor Trace Specification
  ☆203Updated last week
• bluespec / Piccolo
  RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)
  ☆331Updated 4 years ago
• schoeberl / chisel-book
  Digital Design with Chisel
  ☆891Updated 2 months ago
• riscv-non-isa / riscv-toolchain-conventions
  Documenting the expected behaviour and supported command-line switches for GNU and LLVM based RISC-V toolchains
  ☆151Updated 2 weeks ago
• ucb-bar / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆732Updated 4 months ago
• chipsalliance / firrtl
  Flexible Intermediate Representation for RTL
  ☆747Updated last year
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆921Updated 2 years ago
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆648Updated 2 weeks ago
• RoaLogic / RV12
  RISC-V CPU Core
  ☆404Updated 7 months ago
• SpinalHDL / NaxRiscv
  ☆306Updated 2 months ago
• firesim / firesim
  FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility
  ☆989Updated 7 months ago