Alternatives and similar repositories for rvv-bench

Users that are interested in rvv-bench are comparing it to the libraries listed below

• RALC88 / riscv-vectorized-benchmark-suite
  RiVEC Bencmark Suite
  ☆124Updated last year
• IntelLabs / riscv-vector
  Vector Acceleration IP core for RISC-V*
  ☆190Updated 6 months ago
• ucb-bar / saturn-vectors
  Chisel RISC-V Vector 1.0 Implementation
  ☆121Updated 2 months ago
• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆95Updated 3 weeks ago
• riscv / riscv-p-spec
  RISC-V Packed SIMD Extension
  ☆152Updated last month
• XUANTIE-RV / riscv-matrix-extension-spec
  A matrix extension proposal for AI applications under RISC-V architecture
  ☆155Updated 9 months ago
• plctlab / plct-gem5
  upstream: https://github.com/RALC88/gem5
  ☆33Updated 2 years ago
• riscv / riscv-bfloat16
  ☆37Updated last year
• riscv-non-isa / rvv-intrinsic-doc
  ☆351Updated last month
• sparcians / map
  Modeling Architectural Platform
  ☆212Updated this week
• bucaps / marss-riscv
  TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems
  ☆162Updated 3 years ago
• brucehoult / rvv_example
  Simple demonstration of using the RISC-V Vector extension
  ☆49Updated last year
• ucb-bar / hwacha
  Microarchitecture implementation of the decoupled vector-fetch accelerator
  ☆158Updated last year
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆125Updated this week
• tenstorrent / riscv-ocelot
  Ocelot: The Berkeley Out-of-Order Machine With V-EXT support
  ☆198Updated last week
• riscv-non-isa / riscv-iommu
  RISC-V IOMMU Specification
  ☆144Updated last week
• riscv-software-src / riscv-perf-model
  Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model
  ☆191Updated this week
• pulp-platform / snitch_cluster
  An energy-efficient RISC-V floating-point compute cluster.
  ☆114Updated this week
• pulp-platform / hero
  Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…
  ☆113Updated 2 years ago
• camel-cdr / rvv-bench-results
  A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code. (Results)
  ☆40Updated 2 months ago
• riscvarchive / riscv-CMOs
  ☆89Updated 3 months ago
• rivosinc / veclibm
  Vector math library using RISC-V vector ISA via C intrinsic
  ☆22Updated last year
• OpenXiangShan / GEM5
  ☆113Updated this week
• litmus-tests / litmus-tests-riscv
  RISC-V architecture concurrency model litmus tests
  ☆93Updated 6 months ago
• UIUC-ChenLab / scalehls
  A scalable High-Level Synthesis framework on MLIR
  ☆284Updated last year
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆165Updated 5 years ago
• zero-day-labs / riscv-iommu
  IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
  ☆107Updated 2 months ago
• OpenXiangShan / CoupledL2
  Open-source non-blocking L2 cache
  ☆50Updated this week
• EPFL-LAP / dynamatic
  DHLS (Dynamic High-Level Synthesis) compiler based on MLIR
  ☆147Updated this week
• Jerc007 / Open-GPGPU-FlexGrip-
  FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation
  ☆113Updated 2 years ago