camel-cdr / rvv-bench
A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code
☆102Updated last week
Alternatives and similar repositories for rvv-bench:
Users that are interested in rvv-bench are comparing it to the libraries listed below
- RiVEC Bencmark Suite☆109Updated 2 months ago
- Chisel RISC-V Vector 1.0 Implementation☆78Updated this week
- Vector Acceleration IP core for RISC-V*☆166Updated this week
- Unit tests generator for RVV 1.0☆74Updated last week
- RISC-V Packed SIMD Extension☆141Updated last year
- ☆33Updated 7 months ago
- Following the RISC-V IME extension standard, and reusing Vector register resources, these instructions can bring more than a tenfold perf…☆50Updated 6 months ago
- upstream: https://github.com/RALC88/gem5☆31Updated last year
- A matrix extension proposal for AI applications under RISC-V architecture☆124Updated this week
- This is an read-only mirror of the gem5 simulator. The upstream repository is stored in https://gem5.googlesource.com, code reviews shoul…☆11Updated 2 years ago
- A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code. (Results)☆28Updated 2 months ago
- Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model☆149Updated this week
- Simple demonstration of using the RISC-V Vector extension☆40Updated 9 months ago
- ☆308Updated last week
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆89Updated this week
- Modeling Architectural Platform☆176Updated 2 weeks ago
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆149Updated last year
- RISC-V architecture concurrency model litmus tests☆74Updated last year
- Vector math library using RISC-V vector ISA via C intrinsic☆15Updated 3 months ago
- TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems☆147Updated 2 years ago
- ☆151Updated 11 months ago
- Ocelot: The Berkeley Out-of-Order Machine With V-EXT support☆157Updated last month
- FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation☆90Updated last year
- ☆89Updated this week
- Lectures for the Agile Hardware Design course in Jupyter Notebooks☆85Updated 10 months ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆99Updated last year
- Ventus GPGPU ISA Simulator Based on Spike☆40Updated this week
- Documenting the expected behaviour and supported command-line switches for GNU and LLVM based RISC-V toolchains☆148Updated 3 weeks ago
- ☆83Updated 2 years ago
- high-performance RTL simulator☆151Updated 7 months ago