A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code
☆155Aug 14, 2026Updated 2 months ago
Alternatives and similar repositories for rvv-bench
Users that are interested in rvv-bench are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code. (Results)☆51Aug 24, 2026Updated 2 months ago
- Unit tests generator for RVV 1.0☆118May 25, 2026Updated 5 months ago
- RiVEC Bencmark Suite☆134Nov 27, 2024Updated last year
- Vector math library using RISC-V vector ISA via C intrinsic☆26Mar 27, 2026Updated 7 months ago
- Nuclei AI Library Optimized For RISC-V Vector☆16Oct 15, 2025Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Chisel RISC-V Vector 1.0 Implementation☆159Updated this week
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆180Updated this week
- PLCT实验室 rvv-llvm 实现配套的 benchmark / testcases☆21Nov 26, 2020Updated 5 years ago
- Translate RISC-V Vector Assembly from v1.0 to v0.7☆37Aug 21, 2024Updated 2 years ago
- Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model☆226Updated this week
- x86-64, ARM, and RVV intrinsics viewer☆80Sep 10, 2026Updated last month
- ☆382Oct 15, 2026Updated 3 weeks ago
- Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit☆39Dec 23, 2021Updated 4 years ago
- muRISCV-NN is a collection of efficient deep learning kernels for embedded platforms and microcontrollers.☆107Updated this week
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- ☆325Jul 22, 2026Updated 3 months ago
- Vector processor for RISC-V vector ISA☆147Oct 19, 2020Updated 6 years ago
- Original test vector of RISC-V Vector Extension☆14Mar 23, 2021Updated 5 years ago
- A translator from ARM NEON intrinsics to RISCV-V Extension implementation☆44Apr 25, 2026Updated 6 months ago
- Modeling Architectural Platform☆233Oct 29, 2026Updated last week
- SystemVerilog Functional Coverage for RISC-V ISA☆37Dec 11, 2025Updated 10 months ago
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆562Oct 16, 2026Updated 3 weeks ago
- Top project for RISC-V Matrix extension proposal and related opensource implementations.☆39Mar 26, 2024Updated 2 years ago
- A matrix extension proposal for AI applications under RISC-V architecture☆190Apr 1, 2026Updated 7 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- This is a repo for recording and reporting RISCV platform's test and measurement continuously.☆60Dec 19, 2023Updated 2 years ago
- SpacemiT K3 X100 A100 - random snippets from this RISC-V CPU☆25Sep 8, 2026Updated last month
- A Rocket-based RISC-V superscalar in-order core☆42Updated this week
- Working draft of the proposed RISC-V V vector extension☆1,089Mar 17, 2024Updated 2 years ago
- RISC-V Vector (RVV) Automatic Tests Generator with full instructions coverage, including self-checking test and signature test (RISC-V Co…☆17Apr 3, 2024Updated 2 years ago
- This project records the process of optimizing SGEMM (single-precision floating point General Matrix Multiplication) on the riscv platfor…☆24Dec 11, 2024Updated last year
- Ocelot: The Berkeley Out-of-Order Machine With V-EXT support☆265Oct 12, 2026Updated 3 weeks ago
- RISC-V Architecture Profiles☆192Jul 21, 2026Updated 3 months ago
- A Rocket-Chip with a Dynamically Randomized LLC☆13Sep 18, 2024Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- RISC-V RV64GC emulator designed for RTL co-simulation☆244Nov 20, 2024Updated last year
- A simple superscalar out-of-order RISC-V microprocessor☆259Feb 24, 2025Updated last year
- RISC-V IOMMU in verilog☆22Jun 18, 2022Updated 4 years ago
- upstream: https://github.com/RALC88/gem5☆33May 30, 2023Updated 3 years ago
- RISC-V Zve32x Vector Coprocessor☆225Jan 22, 2026Updated 9 months ago
- Sail RISC-V model☆797Updated this week
- Example of RISC-V Vector programming☆31Jul 14, 2026Updated 3 months ago