Alternatives and similar repositories for riscv-isa-sim:

Users that are interested in riscv-isa-sim are comparing it to the libraries listed below

• riscv-software-src / riscv-tools
  RISC-V Tools (ISA Simulator and Tests)
  ☆1,159Updated 2 years ago
• riscv-software-src / riscv-pk
  RISC-V Proxy Kernel
  ☆615Updated this week
• riscv-boom / riscv-boom
  SonicBOOM: The Berkeley Out-of-Order Machine
  ☆1,848Updated last week
• riscv / riscv-opcodes
  RISC-V Opcodes
  ☆735Updated this week
• riscvarchive / riscv-v-spec
  Working draft of the proposed RISC-V V vector extension
  ☆1,012Updated last year
• riscv-collab / riscv-gnu-toolchain
  GNU toolchain for RISC-V, including GCC
  ☆3,818Updated 3 weeks ago
• SpinalHDL / VexRiscv
  A FPGA friendly 32 bit RISC-V CPU implementation
  ☆2,703Updated last month
• riscv-software-src / riscv-tests
  ☆963Updated 3 weeks ago
• YosysHQ / picorv32
  PicoRV32 - A Size-Optimized RISC-V CPU
  ☆3,377Updated 9 months ago
• openhwgroup / cva6
  The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
  ☆2,414Updated this week
• ucb-bar / chipyard
  An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
  ☆1,800Updated this week
• riscv / riscv-isa-manual
  RISC-V Instruction Set Manual
  ☆3,969Updated this week
• chipsalliance / rocket-chip
  Rocket Chip Generator
  ☆3,387Updated last week
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,500Updated last month
• darklife / darkriscv
  opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
  ☆2,251Updated this week
• verilator / verilator
  Verilator open-source SystemVerilog simulator and lint system
  ☆2,790Updated this week
• ultraembedded / riscv
  RISC-V CPU Core (RV32IM)
  ☆1,403Updated 3 years ago
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,081Updated last month
• riscv-software-src / opensbi
  RISC-V Open Source Supervisor Binary Interface
  ☆1,157Updated this week
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,029Updated last month
• riscvarchive / riscv-cores-list
  RISC-V Cores, SoC platforms and SoCs
  ☆868Updated 4 years ago
• riscv-non-isa / riscv-asm-manual
  RISC-V Assembly Programmer's Manual
  ☆1,492Updated 2 weeks ago
• ZipCPU / zipcpu
  A small, light weight, RISC CPU soft core
  ☆1,371Updated last month
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆975Updated 3 years ago
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆864Updated last year
• XUANTIE-RV / openc910
  OpenXuantie - OpenC910 Core
  ☆1,244Updated 9 months ago
• ucb-bar / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆709Updated 3 weeks ago
• olofk / serv
  SERV - The SErial RISC-V CPU
  ☆1,516Updated last week
• riscv-non-isa / riscv-arch-test
  ☆551Updated this week
• llvm / circt
  Circuit IR Compilers and Tools
  ☆1,768Updated this week