Alternatives and similar repositories for riscv-isa-sim

Users that are interested in riscv-isa-sim are comparing it to the libraries listed below

• riscv-software-src / riscv-tools
  RISC-V Tools (ISA Simulator and Tests)
  ☆1,165Updated 2 years ago
• riscv-boom / riscv-boom
  SonicBOOM: The Berkeley Out-of-Order Machine
  ☆1,886Updated last week
• riscv-software-src / riscv-pk
  RISC-V Proxy Kernel
  ☆632Updated 2 weeks ago
• riscvarchive / riscv-v-spec
  Working draft of the proposed RISC-V V vector extension
  ☆1,028Updated last year
• riscv / riscv-opcodes
  RISC-V Opcodes
  ☆760Updated last week
• chipsalliance / rocket-chip
  Rocket Chip Generator
  ☆3,440Updated 3 weeks ago
• riscv-software-src / riscv-tests
  ☆998Updated 2 weeks ago
• riscv-non-isa / riscv-asm-manual
  RISC-V Assembly Programmer's Manual
  ☆1,507Updated last week
• riscv-collab / riscv-gnu-toolchain
  GNU toolchain for RISC-V, including GCC
  ☆3,913Updated this week
• riscv-software-src / opensbi
  RISC-V Open Source Supervisor Binary Interface
  ☆1,191Updated 2 weeks ago
• YosysHQ / picorv32
  PicoRV32 - A Size-Optimized RISC-V CPU
  ☆3,473Updated 10 months ago
• riscv / riscv-isa-manual
  RISC-V Instruction Set Manual
  ☆4,064Updated this week
• ucb-bar / chipyard
  An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
  ☆1,844Updated this week
• darklife / darkriscv
  opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
  ☆2,309Updated last week
• SpinalHDL / VexRiscv
  A FPGA friendly 32 bit RISC-V CPU implementation
  ☆2,756Updated 3 weeks ago
• openhwgroup / cva6
  The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
  ☆2,459Updated this week
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,535Updated last week
• riscvarchive / riscv-cores-list
  RISC-V Cores, SoC platforms and SoCs
  ☆875Updated 4 years ago
• ZipCPU / zipcpu
  A small, light weight, RISC CPU soft core
  ☆1,398Updated 3 months ago
• ultraembedded / riscv
  RISC-V CPU Core (RV32IM)
  ☆1,441Updated 3 years ago
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,065Updated 3 months ago
• ucb-bar / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆713Updated 2 months ago
• olofk / serv
  SERV - The SErial RISC-V CPU
  ☆1,578Updated this week
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆875Updated last year
• chipsalliance / chisel
  Chisel: A Modern Hardware Design Language
  ☆4,265Updated this week
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆1,014Updated 3 years ago
• XUANTIE-RV / openc910
  OpenXuantie - OpenC910 Core
  ☆1,265Updated 10 months ago
• schoeberl / chisel-book
  Digital Design with Chisel
  ☆832Updated last week
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,113Updated 3 months ago
• vortexgpgpu / vortex
  ☆1,508Updated this week