Alternatives and similar repositories for riscv-crypto:

Users that are interested in riscv-crypto are comparing it to the libraries listed below

• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆247Updated 5 months ago
• riscv / riscv-fast-interrupt
  Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
  ☆266Updated this week
• riscv / riscv-bitmanip
  Working draft of the proposed RISC-V Bitmanipulation extension
  ☆210Updated last year
• riscv-non-isa / riscv-trace-spec
  RISC-V Processor Trace Specification
  ☆181Updated 2 weeks ago
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆224Updated 5 months ago
• riscv / sail-riscv
  Sail RISC-V model
  ☆525Updated this week
• riscv / riscv-debug-spec
  Working Draft of the RISC-V Debug Specification Standard
  ☆483Updated last month
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆275Updated last year
• riscv-non-isa / riscv-arch-test
  ☆552Updated 2 weeks ago
• chipsalliance / Cores-VeeR-EH2
  ☆232Updated 2 years ago
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆867Updated last year
• RoaLogic / RV12
  RISC-V CPU Core
  ☆321Updated 10 months ago
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆190Updated 9 months ago
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆521Updated this week
• riscvarchive / riscv-code-size-reduction
  ☆150Updated last year
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆678Updated last month
• pulp-platform / snitch
  ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!
  ☆223Updated last year
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆695Updated last month
• openhwgroup / programs
  Documentation for the OpenHW Group's set of CORE-V RISC-V cores
  ☆208Updated last week
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆229Updated 5 months ago
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆274Updated this week
• pulp-platform / ara
  The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …
  ☆418Updated last month
• SymbioticEDA / riscv-formal
  RISC-V Formal Verification Framework
  ☆596Updated 3 years ago
• bucaps / marss-riscv
  TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems
  ☆151Updated 2 years ago
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆312Updated 4 months ago
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆475Updated 2 months ago
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆250Updated last month
• sifiveinc / freedom-u-sdk
  Freedom U Software Development Kit (FUSDK)
  ☆286Updated this week
• riscv / riscv-profiles
  RISC-V Architecture Profiles
  ☆141Updated 2 months ago
• riscv-ovpsim / imperas-riscv-tests
  ☆171Updated last year