Alternatives and similar repositories for riscv-crypto:

Users that are interested in riscv-crypto are comparing it to the libraries listed below

• riscv / riscv-debug-spec
  Working Draft of the RISC-V Debug Specification Standard
  ☆473Updated this week
• riscv / riscv-bitmanip
  Working draft of the proposed RISC-V Bitmanipulation extension
  ☆208Updated 11 months ago
• riscv-non-isa / riscv-arch-test
  ☆538Updated this week
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆272Updated last year
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆848Updated last year
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆658Updated last week
• riscv / riscv-fast-interrupt
  Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
  ☆258Updated this week
• chipsalliance / Cores-VeeR-EH2
  ☆225Updated 2 years ago
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆243Updated 3 months ago
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆306Updated 2 months ago
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆226Updated 3 months ago
• riscv-software-src / riscv-pk
  RISC-V Proxy Kernel
  ☆605Updated 2 weeks ago
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,010Updated last week
• ucb-bar / riscv-mini
  Simple RISC-V 3-stage Pipeline in Chisel
  ☆559Updated 6 months ago
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆221Updated 3 months ago
• sifive / freedom-u-sdk
  Freedom U Software Development Kit (FUSDK)
  ☆283Updated this week
• riscv-non-isa / riscv-trace-spec
  RISC-V Processor Trace Specification
  ☆170Updated this week
• RoaLogic / RV12
  RISC-V CPU Core
  ☆311Updated 8 months ago
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆667Updated 4 months ago
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆493Updated this week
• riscv / sail-riscv
  Sail RISC-V model
  ☆502Updated this week
• firesim / firesim
  FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility
  ☆906Updated 2 weeks ago
• pulp-platform / ara
  The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …
  ☆398Updated this week
• SymbioticEDA / riscv-formal
  RISC-V Formal Verification Framework
  ☆592Updated 2 years ago
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆263Updated this week
• bluespec / Flute
  RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance
  ☆362Updated last year
• riscvarchive / educational-materials
  Educational materials for RISC-V
  ☆224Updated 3 years ago
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,471Updated this week
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,066Updated 2 weeks ago
• riscvarchive / riscv-software-list
  The RISC-V software tools list, as seen on riscv.org
  ☆461Updated 3 years ago