Alternatives and similar repositories for riscv-crypto

Users that are interested in riscv-crypto are comparing it to the libraries listed below

• riscv / riscv-bitmanip
  Working draft of the proposed RISC-V Bitmanipulation extension
  ☆214Updated last year
• riscv / riscv-debug-spec
  Working Draft of the RISC-V Debug Specification Standard
  ☆489Updated last week
• riscv / riscv-fast-interrupt
  Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
  ☆278Updated last week
• riscv-non-isa / riscv-trace-spec
  RISC-V Processor Trace Specification
  ☆194Updated last week
• riscv-non-isa / riscv-arch-test
  ☆597Updated last week
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆295Updated last year
• riscv / sail-riscv
  Sail RISC-V model
  ☆611Updated this week
• riscv / riscv-profiles
  RISC-V Architecture Profiles
  ☆166Updated last month
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆274Updated 2 weeks ago
• riscv-software-src / riscv-pk
  RISC-V Proxy Kernel
  ☆660Updated last week
• riscvarchive / riscv-code-size-reduction
  ☆147Updated last year
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆232Updated 10 months ago
• openhwgroup / programs
  Documentation for the OpenHW Group's set of CORE-V RISC-V cores
  ☆219Updated 4 months ago
• pulp-platform / mempool
  A 256-RISC-V-core system with low-latency access into shared L1 memory.
  ☆305Updated this week
• chipsalliance / Cores-VeeR-EH2
  ☆245Updated 2 years ago
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆730Updated 2 weeks ago
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆245Updated 11 months ago
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆325Updated 9 months ago
• riscv / riscv-opcodes
  RISC-V Opcodes
  ☆804Updated this week
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆297Updated this week
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆738Updated 2 weeks ago
• riscv-non-isa / riscv-toolchain-conventions
  Documenting the expected behaviour and supported command-line switches for GNU and LLVM based RISC-V toolchains
  ☆152Updated last week
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆201Updated last year
• firesim / firesim
  FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility
  ☆968Updated 3 months ago
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆899Updated 2 years ago
• bluespec / Flute
  RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance
  ☆373Updated last year
• SymbioticEDA / riscv-formal
  RISC-V Formal Verification Framework
  ☆612Updated 3 years ago
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆599Updated 2 weeks ago
• bucaps / marss-riscv
  TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems
  ☆159Updated 3 years ago
• RoaLogic / RV12
  RISC-V CPU Core
  ☆386Updated 3 months ago