A matrix extension proposal for AI applications under RISC-V architecture
☆183Apr 1, 2026Updated 3 months ago
Alternatives and similar repositories for riscv-matrix-extension-spec
Users that are interested in riscv-matrix-extension-spec are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- An optimized neural network operator library for chips base on Xuantie CPU.☆102Feb 10, 2026Updated 4 months ago
- RISC-V Matrix Specification☆26Dec 2, 2024Updated last year
- Nuclei AI Library Optimized For RISC-V Vector☆15Oct 15, 2025Updated 8 months ago
- RISC-V Integrated Matrix Development Repository☆25Jun 22, 2026Updated last week
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆526Jun 8, 2026Updated 3 weeks ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- AI-ML-NLP Task Group☆13Aug 10, 2023Updated 2 years ago
- TVM for chips base on Xuantie CPU, an open deep learning compiler stack.☆31Feb 10, 2026Updated 4 months ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆161Updated this week
- GPGPU processor supporting RISCV-V extension, developed with Chisel HDL☆922Jun 27, 2026Updated last week
- matrix-coprocessor for RISC-V☆36Feb 27, 2026Updated 4 months ago
- ☆377Jun 18, 2026Updated 2 weeks ago
- Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit☆39Dec 23, 2021Updated 4 years ago
- Unit tests generator for RVV 1.0☆114May 25, 2026Updated last month
- Chisel RISC-V Vector 1.0 Implementation☆152Apr 23, 2026Updated 2 months ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- ☆319May 13, 2026Updated last month
- A small DNN library for RISC-V, using RISC-V Vector and Matrix extensions☆11Mar 13, 2025Updated last year
- Ocelot: The Berkeley Out-of-Order Machine With V-EXT support☆256Updated this week
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆620May 26, 2026Updated last month
- Vector processor for RISC-V vector ISA☆140Oct 19, 2020Updated 5 years ago
- RISC-V Zve32x Vector Coprocessor☆221Jan 22, 2026Updated 5 months ago
- RISC-V Architecture Profiles☆190Apr 22, 2026Updated 2 months ago
- ☆39Mar 6, 2026Updated 3 months ago
- A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code☆152Jun 11, 2026Updated 3 weeks ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- Input / Output Physical Memory Protection Unit for RISC-V☆15Jul 20, 2023Updated 2 years ago
- Administrative repository for the Attached Matrix Facility Task Group☆14Dec 11, 2023Updated 2 years ago
- Open source high performance IEEE-754 floating unit☆97Feb 26, 2024Updated 2 years ago
- ET Accelerator Firmware and Runtime☆46May 8, 2026Updated last month
- Original test vector of RISC-V Vector Extension☆14Mar 23, 2021Updated 5 years ago
- Open-source non-blocking L2 cache☆63Jun 26, 2026Updated last week
- OpenXuantie - OpenC910 Core☆1,448Jun 28, 2024Updated 2 years ago
- Berkeley's Spatial Array Generator☆1,380Updated this week
- GNU toolchain for Xuantie RISC-V CPU, including GCC and Binutils ……☆116Apr 12, 2025Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆385Jun 14, 2026Updated 3 weeks ago
- ☆156Oct 6, 2023Updated 2 years ago
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,309Jun 26, 2026Updated last week
- RISC-V Opcodes☆865May 20, 2026Updated last month
- ☆63Feb 18, 2019Updated 7 years ago
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆165Jan 25, 2024Updated 2 years ago
- Documentation developer guide☆136Jun 25, 2026Updated last week