Alternatives and similar repositories for riscv-matrix-extension-spec

Users that are interested in riscv-matrix-extension-spec are comparing it to the libraries listed below

• RALC88 / riscv-vectorized-benchmark-suite
  RiVEC Bencmark Suite
  ☆123Updated 10 months ago
• THU-DSP-LAB / ventus-gpgpu-verilog
  GPGPU supporting RISCV-V, developed with verilog HDL
  ☆113Updated 7 months ago
• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆92Updated last week
• OpenXiangShan / GEM5
  ☆103Updated last week
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆211Updated last month
• riscv-stc / riscv-matrix-project
  Top project for RISC-V Matrix extension proposal and related opensource implementations.
  ☆34Updated last year
• ucb-bar / uciedigital
  Pure digital components of a UCIe controller
  ☆71Updated 3 weeks ago
• RV-BOSC / OpenNoC
  ☆195Updated 3 months ago
• ic-lab-duth / RISC-V-Vector
  Vector processor for RISC-V vector ISA
  ☆128Updated 4 years ago
• schoeberl / chisel-lab
  Lab exercises for Chisel in the digital electronics 2 course at DTU
  ☆210Updated 4 months ago
• pulp-platform / ara
  The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …
  ☆462Updated 2 months ago
• tukl-msd / DRAMSys
  DRAMSys a SystemC TLM-2.0 based DRAM simulator.
  ☆306Updated last week
• cnrv / fpga-rocket-chip
  Wrapper for Rocket-Chip on FPGAs
  ☆137Updated 2 years ago
• IntelLabs / riscv-vector
  Vector Acceleration IP core for RISC-V*
  ☆183Updated 4 months ago
• OpenXiangShan / xs-env
  XiangShan Frontend Develop Environment
  ☆66Updated last week
• OSCPU / ysyxSoC
  ☆87Updated 2 weeks ago
• riscv-software-src / riscv-perf-model
  Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model
  ☆189Updated 2 weeks ago
• sparcians / map
  Modeling Architectural Platform
  ☆206Updated this week
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆52Updated 3 years ago
• UCLA-VAST / AutoSA
  AutoSA: Polyhedral-Based Systolic Array Compiler
  ☆225Updated 2 years ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆228Updated this week
• OpenXiangShan / fudian
  Open source high performance IEEE-754 floating unit
  ☆84Updated last year
• plctlab / plct-gem5
  upstream: https://github.com/RALC88/gem5
  ☆33Updated 2 years ago
• vortexgpgpu / vortex_tutorials
  ☆183Updated this week
• ucb-bar / hwacha
  Microarchitecture implementation of the decoupled vector-fetch accelerator
  ☆155Updated last year
• XS-MLVP / picker
  Pick your favorite language to verify your chip.
  ☆70Updated last week
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆175Updated last month
• OpenXiangShan / difftest
  Modern co-simulation framework for RISC-V CPUs
  ☆157Updated this week
• UIUC-ChenLab / scalehls
  A scalable High-Level Synthesis framework on MLIR
  ☆278Updated last year
• ucb-bar / saturn-vectors
  Chisel RISC-V Vector 1.0 Implementation
  ☆112Updated last month