XUANTIE-RV / riscv-matrix-extension-specLinks
A matrix extension proposal for AI applications under RISC-V architecture
☆156Updated 11 months ago
Alternatives and similar repositories for riscv-matrix-extension-spec
Users that are interested in riscv-matrix-extension-spec are comparing it to the libraries listed below
Sorting:
- Unit tests generator for RVV 1.0☆99Updated 2 months ago
- Top project for RISC-V Matrix extension proposal and related opensource implementations.☆35Updated last year
- RiVEC Bencmark Suite☆127Updated last year
- GPGPU supporting RISCV-V, developed with verilog HDL☆135Updated 10 months ago
- ☆122Updated this week
- DRAMSys a SystemC TLM-2.0 based DRAM simulator.☆328Updated last month
- A Chisel RTL generator for network-on-chip interconnects☆223Updated 2 months ago
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆206Updated 5 years ago
- Vector processor for RISC-V vector ISA☆134Updated 5 years ago
- A scalable High-Level Synthesis framework on MLIR☆286Updated last year
- XiangShan Frontend Develop Environment☆68Updated 2 weeks ago
- ☆208Updated 2 months ago
- Wrapper for Rocket-Chip on FPGAs☆138Updated 3 years ago
- Modeling Architectural Platform☆215Updated last week
- ☆215Updated 6 months ago
- upstream: https://github.com/RALC88/gem5☆33Updated 2 years ago
- AutoSA: Polyhedral-Based Systolic Array Compiler☆236Updated 3 years ago
- OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.☆165Updated 2 years ago
- Chisel RISC-V Vector 1.0 Implementation☆126Updated 3 months ago
- An open-source UCIe controller implementation☆81Updated this week
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆163Updated last year
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆150Updated this week
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆54Updated 3 years ago
- Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model☆195Updated last week
- Lab exercises for Chisel in the digital electronics 2 course at DTU☆218Updated last month
- A Fast, Low-Overhead On-chip Network☆259Updated 3 weeks ago
- Modern co-simulation framework for RISC-V CPUs☆166Updated this week
- ☆91Updated 3 months ago
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆482Updated last month
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆114Updated 2 years ago