XUANTIE-RV / riscv-matrix-extension-specView external linksLinks
A matrix extension proposal for AI applications under RISC-V architecture
☆162Feb 11, 2025Updated last year
Alternatives and similar repositories for riscv-matrix-extension-spec
Users that are interested in riscv-matrix-extension-spec are comparing it to the libraries listed below
Sorting:
- AI-ML-NLP Task Group☆13Aug 10, 2023Updated 2 years ago
- An optimized neural network operator library for chips base on Xuantie CPU.☆98Jun 26, 2024Updated last year
- Nuclei AI Library Optimized For RISC-V Vector☆14Oct 15, 2025Updated 3 months ago
- RISC-V Matrix Specification☆23Dec 2, 2024Updated last year
- RISC-V Integrated Matrix Development Repository☆21Jan 22, 2026Updated 3 weeks ago
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆487Nov 27, 2025Updated 2 months ago
- matrix-coprocessor for RISC-V☆30Dec 12, 2025Updated 2 months ago
- GPGPU processor supporting RISCV-V extension, developed with Chisel HDL☆867Jan 31, 2026Updated last week
- Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit☆37Dec 23, 2021Updated 4 years ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆136Feb 6, 2026Updated last week
- ☆363Updated this week
- Chisel RISC-V Vector 1.0 Implementation☆133Oct 4, 2025Updated 4 months ago
- RISC-V Architecture Profiles☆173Updated this week
- A small DNN library for RISC-V, using RISC-V Vector and Matrix extensions☆11Mar 13, 2025Updated 11 months ago
- Ocelot: The Berkeley Out-of-Order Machine With V-EXT support☆229Jan 14, 2026Updated 3 weeks ago
- ☆308Feb 6, 2026Updated last week
- A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code☆143Jan 27, 2026Updated 2 weeks ago
- Unit tests generator for RVV 1.0☆102Nov 11, 2025Updated 3 months ago
- Open-source non-blocking L2 cache☆52Feb 3, 2026Updated last week
- Original test vector of RISC-V Vector Extension☆14Mar 23, 2021Updated 4 years ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆569Oct 21, 2025Updated 3 months ago
- RISC-V Zve32x Vector Coprocessor☆205Jan 22, 2026Updated 3 weeks ago
- ☆38Jul 9, 2024Updated last year
- ET Accelerator Firmware and Runtime☆35Jan 29, 2026Updated 2 weeks ago
- Input / Output Physical Memory Protection Unit for RISC-V☆15Jul 20, 2023Updated 2 years ago
- TVM for chips base on Xuantie CPU, an open deep learning compiler stack.☆30Updated this week
- RV64GC Linux Capable RISC-V Core☆52Oct 20, 2025Updated 3 months ago
- Vector processor for RISC-V vector ISA☆136Oct 19, 2020Updated 5 years ago
- Berkeley's Spatial Array Generator☆1,215Updated this week
- Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model☆209Updated this week
- Open source high performance IEEE-754 floating unit☆89Feb 26, 2024Updated last year
- OpenXuantie - OpenC910 Core☆1,388Jun 28, 2024Updated last year
- Administrative repository for the Attached Matrix Facility Task Group☆13Dec 11, 2023Updated 2 years ago
- ☆42Mar 31, 2025Updated 10 months ago
- RiVEC Bencmark Suite☆127Nov 27, 2024Updated last year
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆163Jan 25, 2024Updated 2 years ago
- ☆58Feb 18, 2019Updated 6 years ago
- ☆367Sep 12, 2025Updated 5 months ago
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,133Feb 6, 2026Updated last week