Alternatives and similar repositories for riscv-elf-psabi-doc

Users that are interested in riscv-elf-psabi-doc are comparing it to the libraries listed below

• riscv-non-isa / riscv-asm-manual

  View on GitHub
  RISC-V Assembly Programmer's Manual
  ☆1,606Feb 10, 2026Updated last week
• riscv-software-src / riscv-pk

  View on GitHub
  RISC-V Proxy Kernel
  ☆688Oct 2, 2025Updated 4 months ago
• riscv-non-isa / riscv-sbi-doc

  View on GitHub
  Documentation for the RISC-V Supervisor Binary Interface
  ☆454Feb 6, 2026Updated last week
• riscv / riscv-isa-manual

  View on GitHub
  RISC-V Instruction Set Manual
  ☆4,496Updated this week
• riscv-software-src / opensbi

  View on GitHub
  RISC-V Open Source Supervisor Binary Interface
  ☆1,377Updated this week
• riscv / riscv-opcodes

  View on GitHub
  RISC-V Opcodes
  ☆836Updated this week
• riscv-collab / riscv-gnu-toolchain

  View on GitHub
  GNU toolchain for RISC-V, including GCC
  ☆4,364Updated this week
• riscv-non-isa / riscv-toolchain-conventions

  View on GitHub
  Documenting the expected behaviour and supported command-line switches for GNU and LLVM based RISC-V toolchains
  ☆151Updated this week
• riscv-non-isa / riscv-c-api-doc

  View on GitHub
  Documentation of the RISC-V C API
  ☆80Feb 10, 2026Updated last week
• NJU-ProjectN / fceux-am

  View on GitHub
  ☆104Nov 17, 2025Updated 3 months ago
• riscvarchive / riscv-eabi-spec

  View on GitHub
  Proposal for new Embedded ABI (EABI) for use in embedded RISC-V systems.
  ☆27Jun 7, 2021Updated 4 years ago
• riscv-software-src / riscv-tests

  View on GitHub
  ☆1,119Jan 22, 2026Updated 3 weeks ago
• riscv-software-src / riscv-isa-sim

  View on GitHub
  Spike, a RISC-V ISA Simulator
  ☆3,020Updated this week
• riscv / riscv-debug-spec

  View on GitHub
  Working Draft of the RISC-V Debug Specification Standard
  ☆504Feb 5, 2026Updated last week
• riscv / riscv-plic-spec

  View on GitHub
  PLIC Specification
  ☆150Feb 6, 2026Updated last week
• riscvarchive / riscv-v-spec

  View on GitHub
  Working draft of the proposed RISC-V V vector extension
  ☆1,069Mar 17, 2024Updated last year
• riscv-boom / riscv-boom

  View on GitHub
  SonicBOOM: The Berkeley Out-of-Order Machine
  ☆2,074Feb 5, 2026Updated last week
• riscv / riscv-profiles

  View on GitHub
  RISC-V Architecture Profiles
  ☆173Updated this week
• riscv-non-isa / riscv-arch-test

  View on GitHub
  ☆650Updated this week
• NJU-ProjectN / nemu

  View on GitHub
  NJU EMUlator, a full system x86/mips32/riscv32/riscv64 emulator for teaching
  ☆1,090Nov 14, 2025Updated 3 months ago
• riscv / riscv-test-env

  View on GitHub
  ☆51Jan 9, 2026Updated last month
• chipsalliance / rocket-chip

  View on GitHub
  Rocket Chip Generator
  ☆3,677Jan 9, 2026Updated last month
• ucb-bar / riscv-mini

  View on GitHub
  Simple RISC-V 3-stage Pipeline in Chisel
  ☆604Aug 9, 2024Updated last year
• riscv-non-isa / rvv-intrinsic-doc

  View on GitHub
  ☆363Updated this week
• jameslzhu / riscv-card

  View on GitHub
  An unofficial assembly reference for RISC-V.
  ☆522Nov 12, 2024Updated last year
• riscv-non-isa / riscv-trace-spec

  View on GitHub
  RISC-V Processor Trace Specification
  ☆207Feb 9, 2026Updated last week
• OSCPU / NutShell

  View on GitHub
  RISC-V SoC designed by students in UCAS
  ☆1,509Jan 14, 2026Updated last month
• riscvarchive / riscv-code-size-reduction

  View on GitHub
  ☆148Feb 29, 2024Updated last year
• ucb-bar / chipyard

  View on GitHub
  An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
  ☆2,138Updated this week
• riscv / riscv-bitmanip

  View on GitHub
  Working draft of the proposed RISC-V Bitmanipulation extension
  ☆216Mar 20, 2024Updated last year
• OpenXiangShan / NEMU

  View on GitHub
  Super fast RISC-V ISA emulator for XiangShan processor
  ☆310Updated this week
• chipsalliance / chisel

  View on GitHub
  Chisel: A Modern Hardware Design Language
  ☆4,567Updated this week
• NJU-ProjectN / ics-pa-gitbook

  View on GitHub
  ☆598Aug 20, 2025Updated 5 months ago
• riscv / riscv-fast-interrupt

  View on GitHub
  Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
  ☆286Feb 9, 2026Updated last week
• shinezyy / micro-arch-training

  View on GitHub
  How to make undergraduates or new graduates ready for advanced computer architecture research or modern CPU design
  ☆626Aug 13, 2024Updated last year
• rustsbi / rustsbi

  View on GitHub
  RISC-V Supervisor Binary Interface (RISC-V SBI) library in Rust; runs on M or HS mode; good support for embedded Rust ecosystem. For bina…
  ☆1,246Feb 10, 2026Updated last week
• riscv / sail-riscv

  View on GitHub
  Sail RISC-V model
  ☆667Updated this week
• riscv-non-isa / riscv-semihosting

  View on GitHub
  ☆32Feb 6, 2026Updated last week
• riscv-collab / riscv-openocd

  View on GitHub
  Fork of OpenOCD that has RISC-V support
  ☆509Oct 9, 2025Updated 4 months ago