plctlab / rvv-benchmarkLinks
PLCT实验室 rvv-llvm 实现配套的 benchmark / testcases
☆22Updated 4 years ago
Alternatives and similar repositories for rvv-benchmark
Users that are interested in rvv-benchmark are comparing it to the libraries listed below
Sorting:
- upstream: https://github.com/RALC88/gem5☆31Updated 2 years ago
- Learn NVDLA by SOMNIA☆33Updated 5 years ago
- Template for projects using the Hwacha data-parallel accelerator☆34Updated 4 years ago
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆28Updated this week
- An Open-Source SCAlable Interface for ISA Extensionsfor RISC-V Processors. New Version:☆16Updated last year
- FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation☆102Updated 2 years ago
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆53Updated 5 years ago
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆37Updated last week
- ☆33Updated 3 months ago
- A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …☆41Updated last year
- RISC-V Integrated Matrix Development Repository☆15Updated 8 months ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆68Updated 11 months ago
- RISC-V Matrix Specification☆22Updated 6 months ago
- Full Support 32bit RISC-V in LLVM and CLANG for Vector Extension☆43Updated 4 years ago
- Ventus GPGPU ISA Simulator Based on Spike☆43Updated last week
- The official NaplesPU hardware code repository☆16Updated 5 years ago
- Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC☆33Updated last week
- cycle accurate Network-on-Chip Simulator☆27Updated 2 years ago
- Original test vector of RISC-V Vector Extension☆12Updated 4 years ago
- Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)☆62Updated 2 years ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆54Updated 4 years ago
- HLS for Networks-on-Chip☆35Updated 4 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆50Updated 7 years ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆22Updated this week
- ☆65Updated last week
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆35Updated 2 years ago
- ☆31Updated 2 months ago
- ☆35Updated 11 months ago
- A RISC-V Symmetric Multiprocessor(SMP) based on TileLink and can run Linux OS☆23Updated 3 weeks ago
- 第一届 RISC-V 中国峰会的幻灯片等资料存放☆37Updated 2 years ago