PLCT实验室 rvv-llvm 实现配套的 benchmark / testcases
☆21Nov 26, 2020Updated 5 years ago
Alternatives and similar repositories for rvv-benchmark
Users that are interested in rvv-benchmark are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- PLCT实验室的 RISC-V V Spec 实现，基于llvm/llvm-project，rkruppe/rvv-llvm 和 https://repo.hca.bsc.es/gitlab/rferrer/llvm-epi-0.8☆161Sep 3, 2025Updated 11 months ago
- A hand-written recursive decent Verilog parser.☆10Jun 28, 2026Updated last month
- Full Support 32bit RISC-V in LLVM and CLANG for Vector Extension☆43Dec 21, 2020Updated 5 years ago
- upstream: https://github.com/RALC88/gem5☆33May 30, 2023Updated 3 years ago
- This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usag…☆23Mar 10, 2026Updated 5 months ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Yet another Linux distro for RISC-V.☆14Dec 25, 2025Updated 7 months ago
- The RTL source for AnyCore RISC-V☆33Mar 18, 2022Updated 4 years ago
- MAC system with IEEE754 compatibility☆14Nov 22, 2023Updated 2 years ago
- A 3d printed case design for Lichee Pi 4A☆11May 13, 2023Updated 3 years ago
- A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code☆154Jul 31, 2026Updated last week
- RISC-V vector extension ISA simulation☆18Jun 11, 2019Updated 7 years ago
- PLCT实验室维护的QEMU仓库。代码放在 plct- 前缀的分支里。☆30Sep 18, 2025Updated 10 months ago
- Example of RISC-V Vector programming☆31Jul 14, 2026Updated 3 weeks ago
- Top project for RISC-V Matrix extension proposal and related opensource implementations.☆39Mar 26, 2024Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- RISC-V Vectorized Bencmark Suite. based on https://github.com/RALC88/riscv-vectorized-benchmark-suite☆12Oct 28, 2022Updated 3 years ago
- Bountysource browser extension.☆14Nov 17, 2016Updated 9 years ago
- ☆36Mar 8, 2023Updated 3 years ago
- A RISC-V core running Debian (and a LoongArch core running Linux).☆23Nov 24, 2025Updated 8 months ago
- An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support …☆52Aug 24, 2024Updated last year
- double_fpu_verilog☆21Jul 17, 2014Updated 12 years ago
- RiVEC Bencmark Suite☆133Nov 27, 2024Updated last year
- ☆378Updated this week
- Unit tests generator for RVV 1.0☆115May 25, 2026Updated 2 months ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Parsing library for BLIF netlists☆19Nov 1, 2024Updated last year
- TVM for chips base on Xuantie CPU, an open deep learning compiler stack.☆31Feb 10, 2026Updated 6 months ago
- Vector processor for RISC-V vector ISA☆142Oct 19, 2020Updated 5 years ago
- ☆16Oct 26, 2017Updated 8 years ago
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆62Feb 17, 2022Updated 4 years ago
- Working draft of the proposed RISC-V V vector extension☆1,089Mar 17, 2024Updated 2 years ago
- RISCV lock-step checker based on Spike☆15Jul 20, 2026Updated 3 weeks ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆32Apr 25, 2016Updated 10 years ago
- Parendi: Thousand-way Parallel RTL Simulation on the Graphcore IPU☆28Nov 26, 2025Updated 8 months ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- An instruction set simulator based on DBT-RISE implementing the RISC-V ISA☆37Updated this week
- A LaTeX beamer template for openSUSE☆10Apr 6, 2019Updated 7 years ago
- C/C++ Dynamic Memory Analyzer (CMA)☆18Jul 29, 2014Updated 12 years ago
- DUTH RISC-V Superscalar Microprocessor☆35Oct 23, 2024Updated last year
- Simple benchmark to compare the performance of a various combination of asyncio event loop and zeromq implementations.☆16Dec 12, 2016Updated 9 years ago
- ☆10Sep 26, 2024Updated last year
- HDF5 Performance Analysis Checklist☆13Dec 23, 2024Updated last year