riscv/riscv-arch-test external links

---

GitHub - View repository

GitHub.dev - Open in online code editor

Star history - Growth chart over time

deps.dev - Dependencies and security vulnerabilities

Gitingest - Export source code for LLM usage

Repomix - Export source code for LLM usage

uithub - Export source code for LLM usage

Close

riscv/riscv-arch-test

Readme badge preview -

If you own this repo, copy the snippet below and add it to your README.md

---

Copy

[![RelatedRepos](https://img.shields.io/badge/related-repos-yellow)](https://relatedrepos.com/gh/riscv/riscv-arch-test)

Close

riscv / riscv-arch-testView on GitHubMore

• External links
• Readme badge

☆660Mar 17, 2026Updated this week

Alternatives and similar repositories for riscv-arch-test

Users that are interested in riscv-arch-test are comparing it to the libraries listed below

• riscv-software-src / riscv-tests

  View on GitHub
  ☆1,137Jan 22, 2026Updated last month
• riscv-software-src / riscof

  View on GitHub
  ☆103Aug 29, 2025Updated 6 months ago
• chipsalliance / riscv-dv

  View on GitHub
  Random instruction generator for RISC-V processor verification
  ☆1,262Mar 5, 2026Updated 2 weeks ago
• riscv / sail-riscv

  View on GitHub
  Sail RISC-V model
  ☆679Updated this week
• riscv / riscv-debug-spec

  View on GitHub
  Working Draft of the RISC-V Debug Specification Standard
  ☆507Updated this week
• riscv-ovpsim / imperas-riscv-tests

  View on GitHub
  ☆197Dec 14, 2023Updated 2 years ago
• SymbioticEDA / riscv-formal

  View on GitHub
  RISC-V Formal Verification Framework
  ☆625Apr 6, 2022Updated 3 years ago
• riscv / riscv-opcodes

  View on GitHub
  RISC-V Opcodes
  ☆841Updated this week
• openhwgroup / core-v-verif

  View on GitHub
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆663Mar 8, 2026Updated last week
• riscv-software-src / riscv-isa-sim

  View on GitHub
  Spike, a RISC-V ISA Simulator
  ☆3,034Feb 26, 2026Updated 3 weeks ago
• chipsalliance / dromajo

  View on GitHub
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆237Nov 20, 2024Updated last year
• riscv-non-isa / riscv-trace-spec

  View on GitHub
  RISC-V Processor Trace Specification
  ☆209Updated this week
• ucb-bar / riscv-torture

  View on GitHub
  RISC-V Torture Test
  ☆214Jul 11, 2024Updated last year
• openhwgroup / cva6

  View on GitHub
  The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…
  ☆2,845Mar 10, 2026Updated last week
• openhwgroup / force-riscv

  View on GitHub
  Instruction Set Generator initially contributed by Futurewei
  ☆305Oct 17, 2023Updated 2 years ago
• riscv-software-src / riscv-isac

  View on GitHub
  ☆34Nov 4, 2024Updated last year
• riscv-software-src / riscv-ctg

  View on GitHub
  ☆41Nov 4, 2024Updated last year
• lowRISC / ibex

  View on GitHub
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,797Feb 17, 2026Updated last month
• riscvarchive / riscv-code-size-reduction

  View on GitHub
  ☆148Feb 29, 2024Updated 2 years ago
• chipsalliance / VeeR-ISS

  View on GitHub
  ☆152Oct 6, 2023Updated 2 years ago
• openhwgroup / cv32e40p

  View on GitHub
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,197May 26, 2025Updated 9 months ago
• riscv-software-src / riscv-config

  View on GitHub
  RISC-V Configuration Validator
  ☆82Mar 28, 2025Updated 11 months ago
• riscv-software-src / riscv-pk

  View on GitHub
  RISC-V Proxy Kernel
  ☆687Oct 2, 2025Updated 5 months ago
• riscv / riscv-test-env

  View on GitHub
  ☆51Jan 9, 2026Updated 2 months ago
• riscv / riscv-bitmanip

  View on GitHub
  Working draft of the proposed RISC-V Bitmanipulation extension
  ☆215Mar 20, 2024Updated 2 years ago
• openhwgroup / programs

  View on GitHub
  Documentation for the OpenHW Group's set of CORE-V RISC-V cores
  ☆224Jan 11, 2026Updated 2 months ago
• rivosinc / hammer

  View on GitHub
  Infrastructure to drive Spike (RISC-V ISA Simulator) in cosim mode. Hammer provides a C++ and Python interface to interact with Spike.
  ☆39Jan 19, 2026Updated 2 months ago
• riscv / riscv-fast-interrupt

  View on GitHub
  Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
  ☆289Updated this week
• riscv / riscv-isa-manual

  View on GitHub
  RISC-V Instruction Set Manual
  ☆4,529Updated this week
• riscv-verification / RVVI

  View on GitHub
  RISC-V Verification Interface
  ☆145Mar 6, 2026Updated 2 weeks ago
• riscv / riscv-crypto

  View on GitHub
  RISC-V cryptography extensions standardisation work.
  ☆407Mar 7, 2026Updated last week
• riscvarchive / riscv-CMOs

  View on GitHub
  ☆89Aug 26, 2025Updated 6 months ago
• riscv-boom / riscv-boom

  View on GitHub
  SonicBOOM: The Berkeley Out-of-Order Machine
  ☆2,105Mar 11, 2026Updated last week
• riscv-non-isa / riscv-asm-manual

  View on GitHub
  RISC-V Assembly Programmer's Manual
  ☆1,620Updated this week
• ultraembedded / biriscv

  View on GitHub
  32-bit Superscalar RISC-V CPU
  ☆1,191Sep 18, 2021Updated 4 years ago
• olofk / serv

  View on GitHub
  SERV - The SErial RISC-V CPU
  ☆1,766Feb 19, 2026Updated last month
• riscv-collab / riscv-gnu-toolchain

  View on GitHub
  GNU toolchain for RISC-V, including GCC
  ☆4,394Mar 13, 2026Updated last week
• openhwgroup / cvfpu

  View on GitHub
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆577Mar 11, 2026Updated last week
• riscv / riscv-profiles

  View on GitHub
  RISC-V Architecture Profiles
  ☆177Mar 13, 2026Updated last week