Alternatives and similar repositories for riscv-tests

Users that are interested in riscv-tests are comparing it to the libraries listed below

• riscv-non-isa / riscv-arch-test
  ☆611Updated this week
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,206Updated 2 months ago
• riscv / riscv-opcodes
  RISC-V Opcodes
  ☆813Updated 2 weeks ago
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆1,132Updated 4 years ago
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,144Updated 6 months ago
• ucb-bar / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆726Updated 3 months ago
• riscv-software-src / riscv-pk
  RISC-V Proxy Kernel
  ☆669Updated 2 months ago
• riscvarchive / riscv-cores-list
  RISC-V Cores, SoC platforms and SoCs
  ☆905Updated 4 years ago
• riscv-boom / riscv-boom
  SonicBOOM: The Berkeley Out-of-Order Machine
  ☆2,019Updated 6 months ago
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆912Updated 2 years ago
• schoeberl / chisel-book
  Digital Design with Chisel
  ☆878Updated last week
• ucb-bar / riscv-mini
  Simple RISC-V 3-stage Pipeline in Chisel
  ☆601Updated last year
• ultraembedded / riscv
  RISC-V CPU Core (RV32IM)
  ☆1,589Updated 4 years ago
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,686Updated last week
• freechipsproject / chisel-bootcamp
  Generator Bootcamp Material: Learn Chisel the Right Way
  ☆1,086Updated last year
• ucb-bar / chipyard
  An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
  ☆2,044Updated last week
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆748Updated 3 weeks ago
• XUANTIE-RV / openc910
  OpenXuantie - OpenC910 Core
  ☆1,347Updated last year
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆746Updated 2 months ago
• SymbioticEDA / riscv-formal
  RISC-V Formal Verification Framework
  ☆617Updated 3 years ago
• riscv / riscv-debug-spec
  Working Draft of the RISC-V Debug Specification Standard
  ☆500Updated this week
• riscvarchive / riscv-v-spec
  Working draft of the proposed RISC-V V vector extension
  ☆1,053Updated last year
• ucb-bar / chisel-tutorial
  chisel tutorial exercises and answers
  ☆736Updated 3 years ago
• riscv-software-src / riscv-tools
  RISC-V Tools (ISA Simulator and Tests)
  ☆1,170Updated 2 years ago
• chipsalliance / chisel-template
  A template project for beginning new Chisel work
  ☆671Updated 2 months ago
• syntacore / scr1
  SCR1 is a high-quality open-source RISC-V MCU core in Verilog
  ☆942Updated last year
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆676Updated 4 months ago
• rsd-devel / rsd
  RSD: RISC-V Out-of-Order Superscalar Processor
  ☆1,127Updated last month
• olofk / serv
  SERV - The SErial RISC-V CPU
  ☆1,701Updated last month
• ZipCPU / zipcpu
  A small, light weight, RISC CPU soft core
  ☆1,480Updated 3 months ago