Alternatives and similar repositories for riscv-tests:

Users that are interested in riscv-tests are comparing it to the libraries listed below

• riscv-non-isa / riscv-arch-test
  ☆530Updated last week
• riscv-software-src / riscv-pk
  RISC-V Proxy Kernel
  ☆603Updated 3 months ago
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,051Updated 4 months ago
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆999Updated 5 months ago
• riscv / riscv-opcodes
  RISC-V Opcodes
  ☆710Updated last week
• ucb-bar / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆697Updated 5 months ago
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆915Updated 3 years ago
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,441Updated this week
• riscv-boom / riscv-boom
  SonicBOOM: The Berkeley Out-of-Order Machine
  ☆1,784Updated 3 months ago
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆836Updated last year
• ucb-bar / riscv-mini
  Simple RISC-V 3-stage Pipeline in Chisel
  ☆555Updated 5 months ago
• riscvarchive / riscv-cores-list
  RISC-V Cores, SoC platforms and SoCs
  ☆855Updated 3 years ago
• riscv / riscv-debug-spec
  Working Draft of the RISC-V Debug Specification Standard
  ☆468Updated last week
• ucb-bar / chipyard
  An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
  ☆1,721Updated this week
• schoeberl / chisel-book
  Digital Design with Chisel
  ☆795Updated last week
• freechipsproject / chisel-bootcamp
  Generator Bootcamp Material: Learn Chisel the Right Way
  ☆1,000Updated 4 months ago
• ucb-bar / chisel-tutorial
  chisel tutorial exercises and answers
  ☆706Updated 3 years ago
• ultraembedded / riscv
  RISC-V CPU Core (RV32IM)
  ☆1,325Updated 3 years ago
• syntacore / scr1
  SCR1 is a high-quality open-source RISC-V MCU core in Verilog
  ☆887Updated 2 months ago
• riscv-software-src / riscv-tools
  RISC-V Tools (ISA Simulator and Tests)
  ☆1,152Updated 2 years ago
• chipsalliance / firrtl
  Flexible Intermediate Representation for RTL
  ☆734Updated 4 months ago
• chipsalliance / chisel-template
  A template project for beginning new Chisel work
  ☆608Updated last week
• riscvarchive / riscv-v-spec
  Working draft of the proposed RISC-V V vector extension
  ☆992Updated 10 months ago
• SymbioticEDA / riscv-formal
  RISC-V Formal Verification Framework
  ☆591Updated 2 years ago
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆474Updated this week
• riscv / sail-riscv
  Sail RISC-V model
  ☆490Updated this week
• olofk / serv
  SERV - The SErial RISC-V CPU
  ☆1,467Updated 3 weeks ago
• XUANTIE-RV / openc910
  OpenXuantie - OpenC910 Core
  ☆1,194Updated 6 months ago
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆660Updated 3 months ago
• rsd-devel / rsd
  RSD: RISC-V Out-of-Order Superscalar Processor
  ☆1,026Updated 3 weeks ago