☆38Jul 9, 2024Updated last year
Alternatives and similar repositories for riscv-bfloat16
Users that are interested in riscv-bfloat16 are comparing it to the libraries listed below
Sorting:
- The ISA specification for the ZiCondOps extension.☆19Mar 21, 2024Updated last year
- RISC-V Packed SIMD Extension☆159Updated this week
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆162Jan 25, 2024Updated 2 years ago
- This specification is integrated into the Priv. and Unpriv. specifications. This repo is no longer maintained. Please refer to the Priv. …☆96Updated this week
- ☆99Feb 24, 2026Updated last week
- ☆12Feb 15, 2024Updated 2 years ago
- 《关于浮点运算：作为程序员都应该了解什么？》☆27Apr 17, 2018Updated 7 years ago
- ☆364Feb 24, 2026Updated last week
- An Open-Source SCAlable Interface for ISA Extensionsfor RISC-V Processors. New Version:☆17Feb 29, 2024Updated 2 years ago
- ☆18Jul 26, 2024Updated last year
- Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)☆286Feb 22, 2026Updated last week
- RISC-V Architecture Profiles☆175Feb 18, 2026Updated last week
- A matrix extension proposal for AI applications under RISC-V architecture☆164Feb 11, 2025Updated last year
- Wrapper for ETH Ariane Core☆22Sep 2, 2025Updated 6 months ago
- Fast Floating Point Operators for High Level Synthesis☆24Feb 23, 2023Updated 3 years ago
- Simple runtime for Pulp platforms☆51Feb 2, 2026Updated last month
- Documentation of the RISC-V C API☆81Updated this week
- a clone of POCL that includes RISC-V newlib devices support and Vortex☆49Jan 14, 2026Updated last month
- This project records the process of optimizing SGEMM (single-precision floating point General Matrix Multiplication) on the riscv platfor…☆24Dec 11, 2024Updated last year
- ☆89Aug 26, 2025Updated 6 months ago
- This is the fork of CVA6 intended for PULP development.☆22Feb 24, 2026Updated last week
- A mini-app to represent the multipole resonance representation lookup cross section algorithm.☆23Nov 4, 2023Updated 2 years ago
- ☆26Jul 19, 2024Updated last year
- Working draft of the proposed RISC-V Bitmanipulation extension☆216Mar 20, 2024Updated last year
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆224Jan 11, 2026Updated last month
- This repository contains the specification source for the RISC-V IOPMP Specification. This document proposes a Physical Memory Protectio…☆38Updated this week
- The multi-core cluster of a PULP system.☆111Feb 2, 2026Updated last month
- A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow …☆119Feb 24, 2026Updated last week
- Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator☆62Jun 27, 2025Updated 8 months ago
- Working Draft of the RISC-V J Extension Specification☆194Dec 23, 2025Updated 2 months ago
- RISC-V IOMMU Specification☆147Feb 22, 2026Updated last week
- 2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters☆30Jan 29, 2026Updated last month
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆128Jul 11, 2025Updated 7 months ago
- Basic floating-point components for RISC-V processors☆67Dec 4, 2019Updated 6 years ago
- RiVEC Bencmark Suite☆127Nov 27, 2024Updated last year
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆83Feb 5, 2026Updated 3 weeks ago
- RISC-V Zve32x Vector Coprocessor☆207Jan 22, 2026Updated last month
- ☆31Jun 15, 2022Updated 3 years ago
- Summary for Stanford class CS243 - Program Analysis and Optimizations | Winter 2016☆32Mar 14, 2016Updated 9 years ago