riscv / riscv-bfloat16Links
☆37Updated last year
Alternatives and similar repositories for riscv-bfloat16
Users that are interested in riscv-bfloat16 are comparing it to the libraries listed below
Sorting:
- A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code☆120Updated 3 weeks ago
- RiVEC Bencmark Suite☆118Updated 8 months ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆110Updated last year
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆154Updated last year
- RISC-V Matrix Specification☆22Updated 8 months ago
- RISC-V Packed SIMD Extension☆150Updated last year
- A matrix extension proposal for AI applications under RISC-V architecture☆150Updated 5 months ago
- Chisel RISC-V Vector 1.0 Implementation☆106Updated 2 months ago
- ☆89Updated 3 years ago
- FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation☆107Updated 2 years ago
- Unit tests generator for RVV 1.0☆89Updated 2 weeks ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆68Updated last year
- ☆71Updated this week
- ☆92Updated last year
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆171Updated 2 weeks ago
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆41Updated last month
- Vector Acceleration IP core for RISC-V*☆181Updated 2 months ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆113Updated this week
- Software workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim.☆85Updated 2 months ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆57Updated 3 years ago
- RiscyOO: RISC-V Out-of-Order Processor☆159Updated 5 years ago
- ☆59Updated this week
- Fork of upstream onnxruntime focused on supporting risc-v accelerators☆88Updated 2 years ago
- The multi-core cluster of a PULP system.☆105Updated last week
- An Open-Source SCAlable Interface for ISA Extensionsfor RISC-V Processors. New Version:☆16Updated last year
- Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator☆60Updated last month
- Simple runtime for Pulp platforms☆48Updated last week
- This project records the process of optimizing SGEMM (single-precision floating point General Matrix Multiplication) on the riscv platfor…☆22Updated 7 months ago
- ☆52Updated 2 weeks ago
- The OpenPiton Platform☆29Updated 2 years ago