☆38Mar 6, 2026Updated 2 weeks ago
Alternatives and similar repositories for riscv-bfloat16
Users that are interested in riscv-bfloat16 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- The ISA specification for the ZiCondOps extension.☆19Mar 21, 2024Updated 2 years ago
- RISC-V Packed SIMD Extension☆161Updated this week
- This specification is integrated into the Priv. and Unpriv. specifications. This repo is no longer maintained. Please refer to the Priv. …☆96Updated this week
- Main Repo for the OpenHW Group Software Task Group☆17Mar 11, 2025Updated last year
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆164Jan 25, 2024Updated 2 years ago
- ☆99Mar 14, 2026Updated last week
- Documenting the expected behaviour and supported command-line switches for GNU and LLVM based RISC-V toolchains☆151Updated this week
- 《关于浮点运算:作为程序员都应该了解什么?》☆27Apr 17, 2018Updated 7 years ago
- This repository contains the specification source for the RISC-V IOPMP Specification. This document proposes a Physical Memory Protectio…☆38Mar 7, 2026Updated 2 weeks ago
- RISC-V Architecture Profiles☆177Mar 13, 2026Updated last week
- Documentation of the RISC-V C API☆84Updated this week
- ☆365Mar 16, 2026Updated last week
- RISC-V Matrix Specification☆23Dec 2, 2024Updated last year
- 我从动漫中学习到的知识和人生感悟☆16Mar 6, 2025Updated last year
- Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)☆290Updated this week
- ☆10Oct 15, 2021Updated 4 years ago
- A matrix extension proposal for AI applications under RISC-V architecture☆165Feb 11, 2025Updated last year
- Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit☆38Dec 23, 2021Updated 4 years ago
- ☆18Jul 26, 2024Updated last year
- RISC-V backports for binutils-gdb. Development is done upstream at the FSF.☆151Jul 7, 2022Updated 3 years ago
- RTL blocks compatible with the Rocket Chip Generator☆17Mar 30, 2025Updated 11 months ago
- Working draft of the proposed RISC-V Bitmanipulation extension☆215Mar 20, 2024Updated 2 years ago
- RISC-V Nexus Trace TG documentation and reference code☆57Mar 14, 2026Updated last week
- Working Draft of the RISC-V J Extension Specification☆194Mar 6, 2026Updated 2 weeks ago
- ☆148Feb 29, 2024Updated 2 years ago
- SMT-LIB benchmarks for shape computations from deep learning models in PyTorch☆18Dec 21, 2022Updated 3 years ago
- A small DNN library for RISC-V, using RISC-V Vector and Matrix extensions☆11Mar 13, 2025Updated last year
- PCB libraries and templates for rocket-chip based FPGA/ASIC designs☆16Feb 24, 2026Updated last month
- An Open-Source SCAlable Interface for ISA Extensionsfor RISC-V Processors. New Version:☆17Feb 29, 2024Updated 2 years ago
- This project records the process of optimizing SGEMM (single-precision floating point General Matrix Multiplication) on the riscv platfor…☆24Dec 11, 2024Updated last year
- Working draft of the proposed RISC-V V vector extension☆1,072Mar 17, 2024Updated 2 years ago
- 2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters☆30Jan 29, 2026Updated last month
- OpenGL ES 1.0/1.1 3D graphics software emulator☆22Jul 14, 2024Updated last year
- Provides dot visualizations of chisel/firrtl circuites☆13Mar 12, 2019Updated 7 years ago
- ☆26Jul 19, 2024Updated last year
- A model compilation solution for various hardware☆467Aug 20, 2025Updated 7 months ago
- A submodule of Chipyard https://github.com/ucb-bar/chipyard☆20Oct 22, 2025Updated 5 months ago
- An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support …☆50Aug 24, 2024Updated last year
- An optimized neural network operator library for chips base on Xuantie CPU.☆99Feb 10, 2026Updated last month