RISC-V Packed SIMD Extension
☆184Oct 28, 2026Updated last week
Alternatives and similar repositories for riscv-p-spec
Users that are interested in riscv-p-spec are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆40Mar 6, 2026Updated 8 months ago
- Working draft of the proposed RISC-V V vector extension☆1,089Mar 17, 2024Updated 2 years ago
- Working draft of the proposed RISC-V Bitmanipulation extension☆221Mar 20, 2024Updated 2 years ago
- ☆143Feb 29, 2024Updated 2 years ago
- ☆382Oct 15, 2026Updated 3 weeks ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- GCC for Xuantie RISC-V CPU, the GNU Compiler Collection.☆22Sep 16, 2026Updated last month
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆163Oct 31, 2024Updated 2 years ago
- The ISA specification for the ZiCondOps extension.☆18Mar 21, 2024Updated 2 years ago
- ☆90Aug 26, 2025Updated last year
- Working Draft of the RISC-V J Extension Specification☆198Mar 6, 2026Updated 8 months ago
- pulp_soc is the core building component of PULP based SoCs☆87Jul 17, 2026Updated 3 months ago
- RISC-V Debug Specification Standard☆530Aug 26, 2026Updated 2 months ago
- The RISC-V Architectural Certification Tests (ACTs) are a set of assembly language tests designed to certify that a design faithfully imp…☆807Updated this week
- RISC-V Architecture Profiles☆192Jul 21, 2026Updated 3 months ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- ☆43Nov 4, 2024Updated 2 years ago
- Sail RISC-V model☆797Updated this week
- Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)☆302Updated this week
- ☆1,258Oct 19, 2026Updated 2 weeks ago
- Documentation of the RISC-V C API☆89Oct 5, 2026Updated last month
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆562Oct 16, 2026Updated 3 weeks ago
- A matrix extension proposal for AI applications under RISC-V architecture☆190Apr 1, 2026Updated 7 months ago
- RISC-V backports for binutils-gdb. Development is done upstream at the FSF.☆152Jul 7, 2022Updated 4 years ago
- Spike, a RISC-V ISA Simulator☆3,273Updated this week
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆232Jan 11, 2026Updated 9 months ago
- This specification is integrated into the Priv. and Unpriv. specifications. This repo is no longer maintained. Please refer to the Priv. …☆98Oct 5, 2026Updated last month
- RISC-V cryptography extensions standardisation work.☆411Mar 7, 2026Updated 7 months ago
- Documenting the expected behaviour and supported command-line switches for GNU and LLVM based RISC-V toolchains☆152Oct 5, 2026Updated last month
- RISC-V Configuration Validator☆82Apr 16, 2026Updated 6 months ago
- Ibex RISC-V core extended with hardware acceleration of cryptography functions☆14May 10, 2024Updated 2 years ago
- RSD: RISC-V Out-of-Order Superscalar Processor☆1,215Updated this week
- RISC-V Opcodes☆887Oct 14, 2026Updated 3 weeks ago
- Nuclei AI Library Optimized For RISC-V Vector☆16Oct 15, 2025Updated last year
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆651Updated this week
- RISC-V Instruction Set Manual☆4,883Updated this week
- ☆367May 22, 2023Updated 3 years ago
- 平头哥玄铁C910的LLVM工具链支持，由PLCT实验室提供，非官方版本☆75Mar 15, 2021Updated 5 years ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions☆27Aug 16, 2023Updated 3 years ago
- RISC-V Matrix Specification☆27Dec 2, 2024Updated last year
- RISC-V Debug Support for our PULP RISC-V Cores☆333Sep 15, 2026Updated last month