riscv / riscv-p-spec
RISC-V Packed SIMD Extension
☆144Updated last year
Alternatives and similar repositories for riscv-p-spec:
Users that are interested in riscv-p-spec are comparing it to the libraries listed below
- ☆150Updated last year
- RISC-V RV64GC emulator designed for RTL co-simulation☆223Updated 4 months ago
- RiVEC Bencmark Suite☆114Updated 4 months ago
- ☆33Updated 8 months ago
- RISC-V Processor Trace Specification☆177Updated this week
- Unit tests generator for RVV 1.0☆79Updated this week
- RISC-V Torture Test☆186Updated 8 months ago
- Working draft of the proposed RISC-V Bitmanipulation extension☆209Updated last year
- ☆85Updated 2 years ago
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆225Updated 4 months ago
- Documenting the expected behaviour and supported command-line switches for GNU and LLVM based RISC-V toolchains☆149Updated last month
- Tile based architecture designed for computing efficiency, scalability and generality☆248Updated 3 weeks ago
- A matrix extension proposal for AI applications under RISC-V architecture☆133Updated last month
- RiscyOO: RISC-V Out-of-Order Processor☆155Updated 4 years ago
- ☆170Updated last year
- Setup scripts and files needed to compile CoreMark on RISC-V☆65Updated 8 months ago
- Chisel RISC-V Vector 1.0 Implementation☆89Updated this week
- Vector Acceleration IP core for RISC-V*☆172Updated this week
- Instruction Set Generator initially contributed by Futurewei☆274Updated last year
- Following the RISC-V IME extension standard, and reusing Vector register resources, these instructions can bring more than a tenfold perf…☆55Updated 7 months ago
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆206Updated 3 weeks ago
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆151Updated last year
- A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code☆108Updated last week
- Ocelot: The Berkeley Out-of-Order Machine With V-EXT support☆158Updated 2 months ago
- Provides various testers for chisel users☆100Updated 2 years ago
- (System)Verilog to Chisel translator☆112Updated 2 years ago
- Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model☆158Updated last week
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆172Updated 8 months ago
- ☆82Updated last week
- RISC-V Debug Support for our PULP RISC-V Cores☆247Updated 4 months ago