Alternatives and similar repositories for riscv-p-spec

Users that are interested in riscv-p-spec are comparing it to the libraries listed below

• riscvarchive / riscv-code-size-reduction
  ☆149Updated last year
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆178Updated 2 months ago
• bucaps / marss-riscv
  TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems
  ☆155Updated 3 years ago
• ucb-bar / saturn-vectors
  Chisel RISC-V Vector 1.0 Implementation
  ☆106Updated 2 months ago
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆229Updated 8 months ago
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆159Updated 5 years ago
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆195Updated last year
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆263Updated last month
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆241Updated 9 months ago
• riscv-non-isa / riscv-trace-spec
  RISC-V Processor Trace Specification
  ☆191Updated this week
• riscv / riscv-bitmanip
  Working draft of the proposed RISC-V Bitmanipulation extension
  ☆214Updated last year
• IntelLabs / riscv-vector
  Vector Acceleration IP core for RISC-V*
  ☆181Updated 2 months ago
• riscv / riscv-CMOs
  ☆89Updated 3 years ago
• ucb-bar / hwacha
  Microarchitecture implementation of the decoupled vector-fetch accelerator
  ☆154Updated last year
• RALC88 / riscv-vectorized-benchmark-suite
  RiVEC Bencmark Suite
  ☆118Updated 8 months ago
• OpenXiangShan / fudian
  Open source high performance IEEE-754 floating unit
  ☆83Updated last year
• OpenXiangShan / HuanCun
  Open-source high-performance non-blocking cache
  ☆87Updated 2 months ago
• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆89Updated 3 weeks ago
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆290Updated last year
• tenstorrent / riscv-ocelot
  Ocelot: The Berkeley Out-of-Order Machine With V-EXT support
  ☆173Updated last week
• SpinalHDL / NaxRiscv
  ☆293Updated last month
• pulp-platform / snitch
  ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!
  ☆226Updated last year
• riscv / riscv-fast-interrupt
  Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
  ☆272Updated last week
• ucb-bar / testchipip
  ☆85Updated last month
• XUANTIE-RV / riscv-matrix-extension-spec
  A matrix extension proposal for AI applications under RISC-V architecture
  ☆150Updated 5 months ago
• riscv-non-isa / riscv-iommu
  RISC-V IOMMU Specification
  ☆125Updated this week
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆171Updated 3 weeks ago
• ucb-bar / berkeley-hardfloat
  ☆334Updated 10 months ago
• riscv-ovpsim / imperas-riscv-tests
  ☆182Updated last year
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆147Updated 9 months ago