riscv / riscv-p-specLinks
RISC-V Packed SIMD Extension
☆146Updated last year
Alternatives and similar repositories for riscv-p-spec
Users that are interested in riscv-p-spec are comparing it to the libraries listed below
Sorting:
- ☆150Updated last year
- RISC-V Torture Test☆195Updated 10 months ago
- Chisel RISC-V Vector 1.0 Implementation☆98Updated 3 weeks ago
- TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems☆152Updated 3 years ago
- ☆86Updated 3 years ago
- Vector Acceleration IP core for RISC-V*☆178Updated 3 weeks ago
- RISC-V IOMMU Specification☆118Updated 3 weeks ago
- Documenting the expected behaviour and supported command-line switches for GNU and LLVM based RISC-V toolchains☆151Updated last week
- RiVEC Bencmark Suite☆116Updated 6 months ago
- RISC-V Processor Trace Specification☆182Updated 2 weeks ago
- Unit tests generator for RVV 1.0☆85Updated 3 weeks ago
- RISC-V RV64GC emulator designed for RTL co-simulation☆229Updated 6 months ago
- Working draft of the proposed RISC-V Bitmanipulation extension☆211Updated last year
- ☆175Updated last year
- Tile based architecture designed for computing efficiency, scalability and generality☆257Updated 2 weeks ago
- Provides various testers for chisel users☆100Updated 2 years ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆68Updated 10 months ago
- A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code☆115Updated last month
- ☆35Updated 10 months ago
- A matrix extension proposal for AI applications under RISC-V architecture☆148Updated 3 months ago
- PLIC Specification☆140Updated 2 years ago
- Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)☆268Updated this week
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆238Updated 6 months ago
- Modeling Architectural Platform☆190Updated this week
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆154Updated last year
- RISC-V Architecture Profiles☆150Updated 3 months ago
- Instruction Set Generator initially contributed by Futurewei☆284Updated last year
- IOMMU IP compliant with the RISC-V IOMMU Specification v1.0☆94Updated 2 months ago
- RiscyOO: RISC-V Out-of-Order Processor☆156Updated 4 years ago
- ☆42Updated 3 years ago