⛔ DEPRECATED ⛔ Lean but mean RISC-V system!
☆229Nov 22, 2023Updated 2 years ago
Alternatives and similar repositories for snitch
Users that are interested in snitch are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- An energy-efficient RISC-V floating-point compute cluster.☆129Apr 24, 2026Updated last week
- A scalable 256/1024-RISC-V-core system with low-latency access into shared L1 memory.☆318Apr 15, 2026Updated 2 weeks ago
- A SystemVerilog source file pickler.☆61Oct 20, 2024Updated last year
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆511Apr 24, 2026Updated last week
- 2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters☆31Jan 29, 2026Updated 3 months ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆149Updated this week
- The multi-core cluster of a PULP system.☆113Mar 28, 2026Updated last month
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆115Sep 18, 2023Updated 2 years ago
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆224Jan 11, 2026Updated 3 months ago
- A Fast, Low-Overhead On-chip Network☆288Updated this week
- Common SystemVerilog components☆738Updated this week
- This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…☆475Apr 16, 2026Updated 2 weeks ago
- whatever it means☆16Apr 1, 2026Updated last month
- Functional verification project for the CORE-V family of RISC-V cores.☆674Apr 16, 2026Updated 2 weeks ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,221Apr 17, 2026Updated 2 weeks ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,561Apr 22, 2026Updated last week
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆269Nov 6, 2024Updated last year
- RISC-V RV64GC emulator designed for RTL co-simulation☆240Nov 20, 2024Updated last year
- A dependency management tool for hardware projects.☆365Apr 22, 2026Updated last week
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,859Apr 14, 2026Updated 2 weeks ago
- ☆102Mar 5, 2026Updated last month
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,906Apr 23, 2026Updated last week
- This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…☆546Nov 26, 2024Updated last year
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Generic Register Interface (contains various adapters)☆138Feb 24, 2026Updated 2 months ago
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆203Apr 3, 2026Updated 3 weeks ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆594Apr 20, 2026Updated last week
- Tile based architecture designed for computing efficiency, scalability and generality☆289Mar 30, 2026Updated last month
- VeeR EL2 Core☆334Apr 22, 2026Updated last week
- DUTH RISC-V Superscalar Microprocessor☆34Oct 23, 2024Updated last year
- VeeR EH1 core☆935May 29, 2023Updated 2 years ago
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆330Apr 22, 2026Updated last week
- Instruction Set Generator initially contributed by Futurewei☆308Oct 17, 2023Updated 2 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- ☆17Mar 21, 2026Updated last month
- A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow …☆126Apr 1, 2026Updated last month
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,234Updated this week
- RISC-V Zve32x Vector Coprocessor☆216Jan 22, 2026Updated 3 months ago
- SERV - The SErial RISC-V CPU☆1,791Feb 19, 2026Updated 2 months ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆160Oct 31, 2024Updated last year
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆21Jan 17, 2026Updated 3 months ago