pulp-platform / snitchLinks
⛔ DEPRECATED ⛔ Lean but mean RISC-V system!
☆226Updated last year
Alternatives and similar repositories for snitch
Users that are interested in snitch are comparing it to the libraries listed below
Sorting:
- RISC-V RV64GC emulator designed for RTL co-simulation☆230Updated 9 months ago
- Tile based architecture designed for computing efficiency, scalability and generality☆263Updated 2 months ago
- Ocelot: The Berkeley Out-of-Order Machine With V-EXT support☆174Updated this week
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆179Updated 3 months ago
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆278Updated last week
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆244Updated 9 months ago
- A 256-RISC-V-core system with low-latency access into shared L1 memory.☆303Updated last week
- TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems☆155Updated 3 years ago
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆218Updated 3 months ago
- RISC-V Debug Support for our PULP RISC-V Cores☆270Updated 4 months ago
- RISC-V System on Chip Template☆159Updated last week
- ☆182Updated last year
- Instruction Set Generator initially contributed by Futurewei☆293Updated last year
- Bringup-Bench is a collection of standalone minimal library and system dependence benchmarks useful for bringing up newly designed CPUs, …☆185Updated 4 months ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆150Updated 9 months ago
- Verilog Configurable Cache☆181Updated 8 months ago
- ☆294Updated 2 weeks ago
- VeeR EL2 Core☆294Updated 2 weeks ago
- RiscyOO: RISC-V Out-of-Order Processor☆160Updated 5 years ago
- ☆148Updated last year
- Open-source FPGA research and prototyping framework.☆209Updated last year
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆176Updated this week
- This tool translates synthesizable SystemC code to synthesizable SystemVerilog.☆282Updated 2 weeks ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆114Updated last week
- RISC-V Torture Test☆197Updated last year
- Open-source RTL logic simulator with CUDA acceleration☆208Updated last week
- The multi-core cluster of a PULP system.☆108Updated this week
- ☆107Updated last week
- RISC-V Processor Trace Specification☆192Updated 3 weeks ago
- ☆89Updated 3 years ago