mmicko / cross-fpgaLinks
Cross compile FPGA tools
☆21Updated 4 years ago
Alternatives and similar repositories for cross-fpga
Users that are interested in cross-fpga are comparing it to the libraries listed below
Sorting:
- Standard HyperRAM core for ECP5 written in Litex/Migen☆14Updated 5 years ago
- Simplified environment for litex☆14Updated 4 years ago
- A configurable USB 2.0 device core☆31Updated 5 years ago
- This repository contains iCEBreaker examples for Amaranth HDL.☆39Updated last year
- USB Full-Speed core written in migen/LiteX☆12Updated 5 years ago
- Small footprint and configurable HyperBus core☆13Updated 3 years ago
- shdl6800: A 6800 processor written in SpinalHDL☆26Updated 5 years ago
- Dual MikroBUS board for Upduino 2 FPGA☆18Updated 7 years ago
- Picorv32 SoC that uses only BRAM, not flash memory☆13Updated 6 years ago
- A cheap iCE40 development board, designed on and for Raspberry Pi☆29Updated 6 years ago
- RISC-V Processor written in Amaranth HDL☆39Updated 3 years ago
- Wishbone bridge over SPI☆11Updated 5 years ago
- My pergola FPGA projects☆30Updated 4 years ago
- Open source hardware down to the chip level!☆30Updated 3 years ago
- A reconfigurable logic circuit made of identical rotatable tiles.☆23Updated 3 years ago
- Next-Generation FPGA Place-and-Route☆10Updated 7 years ago
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- Device description files (architecture, timing, configuration bitstream, and general documentation) for EOS S3 MCU+eFPGA SoC☆26Updated 3 years ago
- crap-o-scope scope implementation for icestick☆20Updated 7 years ago
- iCE40 floorplan viewer☆24Updated 7 years ago
- PLEASE MOVE TO PAWSv2☆17Updated 3 years ago
- System on Chip toolkit for nMigen☆19Updated 5 years ago
- ☆44Updated 5 months ago
- Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.☆62Updated 3 years ago
- PicoRV☆44Updated 5 years ago
- There are many RISC V projects on iCE40. This one is mine.☆15Updated 5 years ago
- Programs for the FOMU, DE10NANO and ULX3S FPGA boards, written in Silice https://github.com/sylefeb/Silice☆36Updated 2 years ago
- Finding the bacteria in rotting FPGA designs.☆14Updated 4 years ago
- Small footprint and configurable Inter-Chip communication cores☆60Updated last month
- Open source MPSoC running 620 MIPS (CHStone) of RISC-V (RV32iMC) programms on the ARTY board (XC7A35T).☆21Updated 5 years ago