Alternatives and similar repositories for cv32e40s:

Users that are interested in cv32e40s are comparing it to the libraries listed below

• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆225Updated 4 months ago
• openhwgroup / programs
  Documentation for the OpenHW Group's set of CORE-V RISC-V cores
  ☆206Updated this week
• pulp-platform / register_interface
  Generic Register Interface (contains various adapters)
  ☆110Updated 5 months ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆78Updated this week
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆79Updated this week
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆246Updated 4 months ago
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆222Updated 3 months ago
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆80Updated this week
• openhwgroup / core-v-mcu
  This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
  ☆173Updated last year
• pulp-platform / cheshire
  A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
  ☆230Updated last week
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆240Updated last month
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆85Updated 3 weeks ago
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆273Updated last year
• riscvarchive / riscv-code-size-reduction
  ☆151Updated last year
• ultraembedded / exactstep
  Instruction set simulator for RISC-V, MIPS and ARM-v6m
  ☆94Updated 3 years ago
• rafaelcalcada / riscv-steel
  RISC-V 32-bit microcontroller developed in Verilog
  ☆168Updated 2 weeks ago
• riscv-ovpsim / imperas-riscv-tests
  ☆168Updated last year
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆60Updated 9 months ago
• pulp-platform / pulp-runtime
  Simple runtime for Pulp platforms
  ☆42Updated 2 weeks ago
• IObundle / iob-soc
  RISC-V System on Chip Template
  ☆156Updated this week
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆266Updated this week
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆169Updated 7 months ago
• ee-uet / UETRV-PCore
  Linux Capable 32-bit RISC-V based SoC in System Verilog
  ☆61Updated 4 months ago
• riscv-non-isa / riscv-trace-spec
  RISC-V Processor Trace Specification
  ☆172Updated last week
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆246Updated last week
• chipsalliance / Cores-VeeR-EH2
  ☆229Updated 2 years ago
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆172Updated 3 months ago
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆154Updated 4 years ago
• Lampro-Mellon / LM-RISCV-DV
  An Open-Source Design and Verification Environment for RISC-V
  ☆78Updated 3 years ago
• riscv / riscv-fast-interrupt
  Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
  ☆260Updated this week