4 stage, in-order, secure RISC-V core based on the CV32E40P
☆156Oct 31, 2024Updated last year
Alternatives and similar repositories for cv32e40s
Users that are interested in cv32e40s are comparing it to the libraries listed below
Sorting:
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆259Nov 6, 2024Updated last year
- 4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions☆26Aug 16, 2023Updated 2 years ago
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆195Feb 12, 2026Updated 3 weeks ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆128Jul 11, 2025Updated 7 months ago
- Generic Register Interface (contains various adapters)☆136Feb 24, 2026Updated last week
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆225Jan 11, 2026Updated last month
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆80May 22, 2024Updated last year
- Functional verification project for the CORE-V family of RISC-V cores.☆659Updated this week
- pulp_soc is the core building component of PULP based SoCs☆82Mar 10, 2025Updated 11 months ago
- Instruction Set Generator initially contributed by Futurewei☆306Oct 17, 2023Updated 2 years ago
- The multi-core cluster of a PULP system.☆111Updated this week
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,190May 26, 2025Updated 9 months ago
- CORE-V Family of RISC-V Cores☆332Feb 13, 2025Updated last year
- RISC-V Debug Support for our PULP RISC-V Cores☆297Feb 4, 2026Updated last month
- CV32E40X Design-Verification environment☆16Mar 25, 2024Updated last year
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆571Oct 21, 2025Updated 4 months ago
- VeeR EL2 Core☆318Feb 23, 2026Updated last week
- RISC-V System on Chip Template☆161Aug 18, 2025Updated 6 months ago
- Common SystemVerilog components☆713Feb 26, 2026Updated last week
- ☆148Feb 29, 2024Updated 2 years ago
- RISC-V microcontroller IP core for embedded, FPGA and ASIC applications☆192Updated this week
- ☆258Dec 22, 2022Updated 3 years ago
- FuseSoC-based SoC for VeeR EH1 and EL2☆336Dec 11, 2024Updated last year
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆197Updated this week
- A scalable 256/1024-RISC-V-core system with low-latency access into shared L1 memory.☆314Feb 11, 2026Updated 3 weeks ago
- Working draft of the proposed RISC-V Bitmanipulation extension☆216Mar 20, 2024Updated last year
- Simple runtime for Pulp platforms☆51Feb 2, 2026Updated last month
- A Linux-capable RISC-V multicore for and by the world☆771Feb 9, 2026Updated 3 weeks ago
- VeeR EH1 core☆929May 29, 2023Updated 2 years ago
- This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…☆461May 15, 2025Updated 9 months ago
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,774Feb 17, 2026Updated 2 weeks ago
- ✔️ Port of RISCOF to check NEORV32 for RISC-V ISA compatibility.☆39Feb 22, 2026Updated last week
- SERV - The SErial RISC-V CPU☆1,761Feb 19, 2026Updated 2 weeks ago
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆320Feb 24, 2026Updated last week
- A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow …☆120Feb 24, 2026Updated last week
- ☆652Updated this week
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆963Nov 15, 2024Updated last year
- RISC-V Packed SIMD Extension☆159Feb 27, 2026Updated last week
- 32-bit Superscalar RISC-V CPU☆1,183Sep 18, 2021Updated 4 years ago