openhwgroup / cv32e40sLinks
4 stage, in-order, secure RISC-V core based on the CV32E40P
☆150Updated last year
Alternatives and similar repositories for cv32e40s
Users that are interested in cv32e40s are comparing it to the libraries listed below
Sorting:
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆246Updated last year
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆219Updated this week
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆123Updated 4 months ago
- The multi-core cluster of a PULP system.☆109Updated 2 weeks ago
- RISC-V soft-core microcontroller for FPGA implementation☆186Updated last month
- Generic Register Interface (contains various adapters)☆133Updated last month
- RISC-V Debug Support for our PULP RISC-V Cores☆280Updated last week
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆187Updated last month
- pulp_soc is the core building component of PULP based SoCs☆81Updated 8 months ago
- RISC-V RV64GC emulator designed for RTL co-simulation☆235Updated 11 months ago
- RISC-V System on Chip Template☆159Updated 3 months ago
- RISC-V Processor Trace Specification☆196Updated last month
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆76Updated last year
- ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!☆226Updated last year
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆102Updated 4 years ago
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆299Updated this week
- Simple runtime for Pulp platforms☆49Updated 2 weeks ago
- ☆147Updated last year
- NucleusRV (rv32-imf) - A 32-bit 5 staged pipelined risc-v core.☆75Updated this week
- ☆89Updated 2 months ago
- Linux Capable 32-bit RISC-V based SoC in System Verilog☆60Updated last year
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆186Updated last month
- CORE-V Family of RISC-V Cores☆304Updated 9 months ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆70Updated last week
- A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow …☆114Updated 3 months ago
- 64-bit multicore Linux-capable RISC-V processor☆99Updated 6 months ago
- ☆87Updated 3 weeks ago
- RiscyOO: RISC-V Out-of-Order Processor☆164Updated 5 years ago
- Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)☆280Updated this week
- A scalable 256/1024-RISC-V-core system with low-latency access into shared L1 memory.☆310Updated last week