Alternatives and similar repositories for riscv-fast-interrupt

Users that are interested in riscv-fast-interrupt are comparing it to the libraries listed below

• riscv-non-isa / riscv-trace-spec
  RISC-V Processor Trace Specification
  ☆203Updated last week
• riscv / riscv-plic-spec
  PLIC Specification
  ☆150Updated last week
• riscv / riscv-debug-spec
  Working Draft of the RISC-V Debug Specification Standard
  ☆504Updated last month
• openhwgroup / programs
  Documentation for the OpenHW Group's set of CORE-V RISC-V cores
  ☆223Updated 2 weeks ago
• riscvarchive / riscv-code-size-reduction
  ☆148Updated last year
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆291Updated last month
• riscv-non-isa / riscv-toolchain-conventions
  Documenting the expected behaviour and supported command-line switches for GNU and LLVM based RISC-V toolchains
  ☆151Updated 3 weeks ago
• riscv / riscv-profiles
  RISC-V Architecture Profiles
  ☆171Updated this week
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆255Updated last year
• riscv / riscv-aia
  ☆99Updated 2 weeks ago
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆154Updated last year
• riscv-non-isa / riscv-arch-test
  ☆641Updated this week
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆239Updated last year
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆304Updated 2 years ago
• riscv-non-isa / riscv-iommu
  RISC-V IOMMU Specification
  ☆146Updated this week
• riscvarchive / riscv-CMOs
  ☆89Updated 5 months ago
• riscvarchive / riscv-platform-specs
  RISC-V Profiles and Platform Specification
  ☆116Updated 2 years ago
• riscv / riscv-bitmanip
  Working draft of the proposed RISC-V Bitmanipulation extension
  ☆216Updated last year
• pulp-platform / mempool
  A scalable 256/1024-RISC-V-core system with low-latency access into shared L1 memory.
  ☆312Updated 2 weeks ago
• SpinalHDL / NaxRiscv
  ☆305Updated last week
• RoaLogic / RV12
  RISC-V CPU Core
  ☆405Updated 7 months ago
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆211Updated last year
• riscv-ovpsim / imperas-riscv-tests
  ☆192Updated 2 years ago
• riscv / riscv-p-spec
  RISC-V Packed SIMD Extension
  ☆155Updated last week
• XUANTIE-RV / openc906
  OpenXuantie - OpenC906 Core
  ☆386Updated last year
• riscvarchive / risc-v-getting-started-guide
  The official RISC-V getting started guide
  ☆202Updated last year
• bucaps / marss-riscv
  TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems
  ☆162Updated 3 years ago
• embench / embench-iot
  The main Embench repository
  ☆300Updated last year
• riscvarchive / riscv-binutils-gdb
  RISC-V backports for binutils-gdb. Development is done upstream at the FSF.
  ☆150Updated 3 years ago
• riscv-software-src / riscof
  ☆101Updated 5 months ago