RISC-V Configuration Structure
☆41Oct 30, 2024Updated last year
Alternatives and similar repositories for configuration-structure
Users that are interested in configuration-structure are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- RISC-V Profiles and Platform Specification☆116Sep 6, 2023Updated 2 years ago
- ☆32Apr 8, 2026Updated last month
- Coffer is a RISC-V trusted execution environment developed in Rust.☆20Mar 3, 2022Updated 4 years ago
- ☆91Aug 26, 2025Updated 8 months ago
- PLIC Specification☆152Apr 8, 2026Updated last month
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Working draft of the proposed RISC-V Bitmanipulation extension☆216Mar 20, 2024Updated 2 years ago
- RISC-V Architecture Profiles☆186Apr 22, 2026Updated last month
- ☆42Jan 14, 2022Updated 4 years ago
- Seal5 - Semi-automated LLVM Support for RISC-V Extensions including Autovectorization☆25Mar 29, 2026Updated last month
- [Archived - See https://github.com/rustsbi/rustsbi/] RustSBI prototyper☆12Feb 16, 2025Updated last year
- TIDENet is an ASIC written in Verilog for Tiny Image Detection at Edge with neural networks (TIDENet) using DNNWeaver 2.0, the Google Sky…☆17Jan 30, 2023Updated 3 years ago
- UPduino☆29Mar 30, 2020Updated 6 years ago
- Working Draft of the RISC-V Debug Specification Standard☆513Apr 8, 2026Updated last month
- The preliminary 'RISC-V microcontroller profile' specs; for convenience, use markdown.☆29Feb 15, 2022Updated 4 years ago
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- A Xtext based SystemRDL editor with syntax highlighting and context sensitive help☆12Feb 9, 2024Updated 2 years ago
- My second attempt at a RISC-V CPU with learnings form my previous attempt.☆10Apr 27, 2026Updated 3 weeks ago
- SoC for muntjac☆13Jun 18, 2025Updated 11 months ago
- 32-bit hashing machinery☆14Apr 30, 2026Updated 3 weeks ago
- RISC-V Configuration Validator☆82Apr 16, 2026Updated last month
- [No longer active] A fork of OpenSBI, with software-emulated hypervisor extension support☆43Aug 15, 2025Updated 9 months ago
- A bare-metal application to test specific features of the risc-v hypervisor extension☆45Nov 24, 2025Updated 6 months ago
- ☆148Feb 29, 2024Updated 2 years ago
- ☆38Aug 6, 2022Updated 3 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- A 66-order (67 taps) hamming FIR LPF Filter is to be designed with a cutoff frequency of 200 KHZ for a sampling frequency of 1 MHZ☆15Feb 17, 2023Updated 3 years ago
- Some neorv32 examples for Intel FPGA boards using Quartus II and SEGGER Embedded Studio for RISC-V.☆15Oct 5, 2025Updated 7 months ago
- This specification is integrated into the Priv. and Unpriv. specifications. This repo is no longer maintained. Please refer to the Priv. …☆95Apr 28, 2026Updated 3 weeks ago
- 🌄 RISC-V Ecosystem Landscape: a living document that developers, investors, vendors, researchers and others can use as a resource on the…☆23Updated this week
- A set of synthetic benchmarks used in IEEE RTAS 2016 paper by Prathap et al.,☆19Mar 31, 2026Updated last month
- 4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions☆27Aug 16, 2023Updated 2 years ago
- Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)☆294May 16, 2026Updated last week
- RISC-V IOMMU Specification☆162May 13, 2026Updated last week
- ☆18Aug 20, 2022Updated 3 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Extended QCADesigner with estimation of energy dissipation☆19Aug 17, 2025Updated 9 months ago
- The RAS Error-record Register Interface provides a specification to augment RAS features in RISC-V SOC hardware to standardize reporting …☆11May 1, 2026Updated 3 weeks ago
- Serialize & deserialize device tree binary using serde☆23Dec 4, 2025Updated 5 months ago
- Pipelined RISC-V RV32I Core in Verilog☆41Apr 9, 2023Updated 3 years ago
- Experiments with safe DMA abstractions in Rust☆18Sep 17, 2020Updated 5 years ago
- Workshop on Open-Source EDA Technology (WOSET)☆50Nov 18, 2024Updated last year
- An RISC-V experimental OS☆27Sep 19, 2023Updated 2 years ago