RISC-V Configuration Structure
☆41Oct 30, 2024Updated last year
Alternatives and similar repositories for configuration-structure
Users that are interested in configuration-structure are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- RISC-V Profiles and Platform Specification☆116Sep 6, 2023Updated 3 years ago
- ☆32Jul 21, 2026Updated 2 months ago
- Coffer is a RISC-V trusted execution environment developed in Rust.☆21Mar 3, 2022Updated 4 years ago
- ☆90Aug 26, 2025Updated last year
- RISC-V Processor Trace Specification☆223Oct 5, 2026Updated last week
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- PLIC Specification☆157Jul 20, 2026Updated 2 months ago
- ☆43Jan 14, 2022Updated 4 years ago
- Working draft of the proposed RISC-V Bitmanipulation extension☆221Mar 20, 2024Updated 2 years ago
- RISC-V Architecture Profiles☆192Jul 21, 2026Updated 2 months ago
- Seal5 - Semi-automated LLVM Support for RISC-V Extensions including Autovectorization☆25Sep 7, 2026Updated last month
- [Archived - See https://github.com/rustsbi/rustsbi/] RustSBI prototyper☆12Feb 16, 2025Updated last year
- TIDENet is an ASIC written in Verilog for Tiny Image Detection at Edge with neural networks (TIDENet) using DNNWeaver 2.0, the Google Sky…☆18Jan 30, 2023Updated 3 years ago
- UPduino☆29Mar 30, 2020Updated 6 years ago
- RISC-V Debug Specification Standard☆530Aug 26, 2026Updated last month
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- 32-bit hashing machinery☆16Apr 30, 2026Updated 5 months ago
- A Xtext based SystemRDL editor with syntax highlighting and context sensitive help☆12Feb 9, 2024Updated 2 years ago
- My second attempt at a RISC-V CPU with learnings form my previous attempt.☆11Apr 27, 2026Updated 5 months ago
- RISC-V Configuration Validator☆82Apr 16, 2026Updated 5 months ago
- [No longer active] A fork of OpenSBI, with software-emulated hypervisor extension support☆43Aug 15, 2025Updated last year
- ☆144Feb 29, 2024Updated 2 years ago
- ☆38Aug 6, 2022Updated 4 years ago
- A 66-order (67 taps) hamming FIR LPF Filter is to be designed with a cutoff frequency of 200 KHZ for a sampling frequency of 1 MHZ☆15Feb 17, 2023Updated 3 years ago
- ☆13Apr 24, 2015Updated 11 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- Some neorv32 examples for Intel FPGA boards using Quartus II and SEGGER Embedded Studio for RISC-V.☆16Oct 5, 2025Updated last year
- Implementation of the `embedded-hal` traits for E310x microcontrollers☆17Apr 1, 2024Updated 2 years ago
- This specification is integrated into the Priv. and Unpriv. specifications. This repo is no longer maintained. Please refer to the Priv. …☆97Oct 5, 2026Updated last week
- A set of synthetic benchmarks used in IEEE RTAS 2016 paper by Prathap et al.,☆19Sep 21, 2026Updated 3 weeks ago
- BFS maze solving program☆14Nov 18, 2018Updated 7 years ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions☆27Aug 16, 2023Updated 3 years ago
- Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)☆302Oct 5, 2026Updated last week
- Pipelined RISC-V RV32I Core in Verilog☆43Apr 9, 2023Updated 3 years ago
- Extended QCADesigner with estimation of energy dissipation☆20Aug 17, 2025Updated last year
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- ☆18Aug 20, 2022Updated 4 years ago
- The RAS Error-record Register Interface provides a specification to augment RAS features in RISC-V SOC hardware to standardize reporting …☆11Oct 2, 2026Updated last week
- The RISC-V External Debug Security Specification☆20Oct 5, 2026Updated last week
- Serialize & deserialize device tree binary using serde☆23Dec 4, 2025Updated 10 months ago
- Experiments with safe DMA abstractions in Rust☆18Sep 17, 2020Updated 6 years ago
- Example litex Risc-V SOC and some example code projects in multiple languages.☆72May 24, 2026Updated 4 months ago
- Workshop on Open-Source EDA Technology (WOSET)☆50Nov 18, 2024Updated last year