Alternatives and similar repositories for riscv-toolchain-conventions:

Users that are interested in riscv-toolchain-conventions are comparing it to the libraries listed below

• riscv / riscv-fast-interrupt
  Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
  ☆258Updated last month
• riscvarchive / riscv-code-size-reduction
  ☆151Updated 11 months ago
• riscv-non-isa / riscv-trace-spec
  RISC-V Processor Trace Specification
  ☆170Updated this week
• riscv-non-isa / riscv-c-api-doc
  Documentation of the RISC-V C API
  ☆75Updated this week
• riscv / riscv-profiles
  RISC-V Architecture Profiles
  ☆133Updated last week
• sifive / freedom-metal
  Bare Metal Compatibility Library for the Freedom Platform
  ☆156Updated last year
• riscv / riscv-CMOs
  ☆84Updated 2 years ago
• riscv / riscv-plic-spec
  PLIC Specification
  ☆139Updated last year
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆221Updated 3 months ago
• riscv / riscv-bitmanip
  Working draft of the proposed RISC-V Bitmanipulation extension
  ☆208Updated 11 months ago
• bucaps / marss-riscv
  TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems
  ☆147Updated 2 years ago
• riscv-non-isa / riscv-iommu
  RISC-V IOMMU Specification
  ☆103Updated this week
• riscvarchive / riscv-platform-specs
  RISC-V Profiles and Platform Specification
  ☆113Updated last year
• riscvarchive / riscv-binutils-gdb
  RISC-V backports for binutils-gdb. Development is done upstream at the FSF.
  ☆149Updated 2 years ago
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆179Updated 7 months ago
• riscv / riscv-aia
  ☆86Updated 3 months ago
• riscv / riscv-p-spec
  RISC-V Packed SIMD Extension
  ☆141Updated last year
• openhwgroup / programs
  Documentation for the OpenHW Group's set of CORE-V RISC-V cores
  ☆205Updated last week
• michaeljclark / riscv-probe
  Simple machine mode program to probe RISC-V control and status registers
  ☆118Updated last year
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆226Updated 3 months ago
• riscv-ovpsim / imperas-riscv-tests
  ☆168Updated last year
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆142Updated 3 months ago
• litmus-tests / litmus-tests-riscv
  RISC-V architecture concurrency model litmus tests
  ☆74Updated last year
• riscv-software-src / riscof
  ☆71Updated 4 months ago
• riscv / riscv-debug-spec
  Working Draft of the RISC-V Debug Specification Standard
  ☆472Updated this week
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆243Updated 3 months ago
• riscv-non-isa / riscv-arch-test
  ☆537Updated this week
• riscv / riscv-test-env
  ☆45Updated last month
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆272Updated last year
• riscv / riscv-aclint
  ☆42Updated 3 years ago