Alternatives and similar repositories for riscv-toolchain-conventions

Users that are interested in riscv-toolchain-conventions are comparing it to the libraries listed below

• riscvarchive / riscv-code-size-reduction
  ☆149Updated last year
• riscv / riscv-fast-interrupt
  Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
  ☆269Updated this week
• riscv-non-isa / riscv-trace-spec
  RISC-V Processor Trace Specification
  ☆187Updated 3 weeks ago
• riscv / riscv-profiles
  RISC-V Architecture Profiles
  ☆154Updated 5 months ago
• riscv / riscv-bitmanip
  Working draft of the proposed RISC-V Bitmanipulation extension
  ☆211Updated last year
• riscv-non-isa / riscv-c-api-doc
  Documentation of the RISC-V C API
  ☆76Updated this week
• riscv / riscv-plic-spec
  PLIC Specification
  ☆142Updated 2 years ago
• riscvarchive / riscv-platform-specs
  RISC-V Profiles and Platform Specification
  ☆113Updated last year
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆229Updated 7 months ago
• riscv / riscv-CMOs
  ☆86Updated 3 years ago
• riscv / riscv-debug-spec
  Working Draft of the RISC-V Debug Specification Standard
  ☆486Updated 2 months ago
• riscv-non-isa / riscv-iommu
  RISC-V IOMMU Specification
  ☆123Updated last week
• riscv / riscv-p-spec
  RISC-V Packed SIMD Extension
  ☆148Updated last year
• bucaps / marss-riscv
  TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems
  ☆154Updated 3 years ago
• riscvarchive / riscv-binutils-gdb
  RISC-V backports for binutils-gdb. Development is done upstream at the FSF.
  ☆149Updated 3 years ago
• riscv / riscv-aia
  ☆89Updated 3 months ago
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆240Updated 8 months ago
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆146Updated 8 months ago
• riscv-ovpsim / imperas-riscv-tests
  ☆181Updated last year
• michaeljclark / riscv-probe
  Simple machine mode program to probe RISC-V control and status registers
  ☆122Updated 2 years ago
• riscvarchive / risc-v-getting-started-guide
  The official RISC-V getting started guide
  ☆202Updated last year
• embench / embench-iot
  The main Embench repository
  ☆284Updated 10 months ago
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆260Updated 2 months ago
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆196Updated last year
• riscv-software-src / riscv-perf-model
  Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model
  ☆180Updated last week
• openhwgroup / programs
  Documentation for the OpenHW Group's set of CORE-V RISC-V cores
  ☆217Updated last month
• riscv-software-src / riscof
  ☆83Updated 3 months ago
• litmus-tests / litmus-tests-riscv
  RISC-V architecture concurrency model litmus tests
  ☆81Updated last month
• riscv-non-isa / riscv-arch-test
  ☆577Updated this week
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆289Updated last year