Alternatives and similar repositories for riscv-trace-spec:

Users that are interested in riscv-trace-spec are comparing it to the libraries listed below

• riscv / riscv-fast-interrupt
  Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
  ☆254Updated last week
• openhwgroup / programs
  Documentation for the OpenHW Group's set of CORE-V RISC-V cores
  ☆203Updated this week
• riscvarchive / riscv-code-size-reduction
  ☆151Updated 10 months ago
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆236Updated 2 months ago
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆225Updated 2 months ago
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆220Updated last month
• riscv / riscv-bitmanip
  Working draft of the proposed RISC-V Bitmanipulation extension
  ☆207Updated 9 months ago
• sifive / sifive-blocks
  Common RTL blocks used in SiFive's projects
  ☆180Updated 2 years ago
• riscv / riscv-debug-spec
  Working Draft of the RISC-V Debug Specification Standard
  ☆468Updated last week
• riscv-non-isa / riscv-iommu
  RISC-V IOMMU Specification
  ☆101Updated 3 weeks ago
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆138Updated 2 months ago
• riscv-non-isa / riscv-toolchain-conventions
  Documenting the expected behaviour and supported command-line switches for GNU and LLVM based RISC-V toolchains
  ☆147Updated 3 weeks ago
• riscv / riscv-aia
  ☆85Updated 2 months ago
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆271Updated last year
• riscv / riscv-CMOs
  ☆82Updated 2 years ago
• riscv-ovpsim / imperas-riscv-tests
  ☆166Updated last year
• sifive / freedom-metal
  Bare Metal Compatibility Library for the Freedom Platform
  ☆155Updated last year
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆257Updated this week
• riscv / riscv-plic-spec
  PLIC Specification
  ☆137Updated last year
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆175Updated 6 months ago
• RoaLogic / RV12
  RISC-V CPU Core
  ☆302Updated 7 months ago
• riscv / riscv-profiles
  RISC-V Architecture Profiles
  ☆125Updated last month
• chipsalliance / Cores-VeeR-EH2
  ☆220Updated 2 years ago
• riscv / riscv-p-spec
  RISC-V Packed SIMD Extension
  ☆141Updated last year
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆153Updated 4 years ago
• pulp-platform / mempool
  A 256-RISC-V-core system with low-latency access into shared L1 memory.
  ☆280Updated last week
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆215Updated 11 months ago
• SpinalHDL / NaxRiscv
  ☆270Updated last month
• bucaps / marss-riscv
  TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems
  ☆146Updated 2 years ago
• riscvarchive / riscv-platform-specs
  RISC-V Profiles and Platform Specification
  ☆113Updated last year