Alternatives and similar repositories for riscv-trace-spec

Users that are interested in riscv-trace-spec are comparing it to the libraries listed below

• riscv / riscv-fast-interrupt
  Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
  ☆272Updated last week
• openhwgroup / programs
  Documentation for the OpenHW Group's set of CORE-V RISC-V cores
  ☆218Updated 2 months ago
• riscvarchive / riscv-code-size-reduction
  ☆149Updated last year
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆265Updated 3 months ago
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆240Updated 8 months ago
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆229Updated 8 months ago
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆147Updated 9 months ago
• riscv / riscv-debug-spec
  Working Draft of the RISC-V Debug Specification Standard
  ☆491Updated 2 months ago
• riscv / riscv-bitmanip
  Working draft of the proposed RISC-V Bitmanipulation extension
  ☆214Updated last year
• riscv-non-isa / riscv-iommu
  RISC-V IOMMU Specification
  ☆125Updated this week
• riscv-software-src / riscof
  ☆84Updated 4 months ago
• riscv / riscv-profiles
  RISC-V Architecture Profiles
  ☆160Updated 5 months ago
• RoaLogic / RV12
  RISC-V CPU Core
  ☆359Updated last month
• riscv / riscv-CMOs
  ☆89Updated 3 years ago
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆195Updated last year
• riscv / riscv-plic-spec
  PLIC Specification
  ☆144Updated 2 years ago
• riscv-non-isa / riscv-toolchain-conventions
  Documenting the expected behaviour and supported command-line switches for GNU and LLVM based RISC-V toolchains
  ☆152Updated this week
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆290Updated last year
• riscv-ovpsim / imperas-riscv-tests
  ☆182Updated last year
• bucaps / marss-riscv
  TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems
  ☆155Updated 3 years ago
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆159Updated 5 years ago
• riscv / riscv-p-spec
  RISC-V Packed SIMD Extension
  ☆150Updated last year
• chipsalliance / Cores-VeeR-EH2
  ☆240Updated 2 years ago
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆292Updated 2 weeks ago
• SpinalHDL / NaxRiscv
  ☆293Updated 3 weeks ago
• rafaelcalcada / rvx
  RISC-V microcontroller IP core developed in Verilog
  ☆175Updated 3 months ago
• pulp-platform / cheshire
  A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
  ☆271Updated last week
• riscv / riscv-aia
  ☆92Updated this week
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆283Updated 5 months ago
• pulp-platform / snitch
  ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!
  ☆226Updated last year