Alternatives and similar repositories for riscv-trace-spec

Users that are interested in riscv-trace-spec are comparing it to the libraries listed below

• riscv / riscv-fast-interrupt
  Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
  ☆280Updated last week
• openhwgroup / programs
  Documentation for the OpenHW Group's set of CORE-V RISC-V cores
  ☆219Updated 5 months ago
• riscvarchive / riscv-code-size-reduction
  ☆147Updated last year
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆235Updated 11 months ago
• riscv / riscv-debug-spec
  Working Draft of the RISC-V Debug Specification Standard
  ☆496Updated last week
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆245Updated last year
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆278Updated last month
• riscv / riscv-bitmanip
  Working draft of the proposed RISC-V Bitmanipulation extension
  ☆215Updated last year
• riscv / riscv-profiles
  RISC-V Architecture Profiles
  ☆166Updated last week
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆202Updated last year
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆150Updated last year
• riscv / riscv-aia
  ☆96Updated 2 months ago
• riscv-ovpsim / imperas-riscv-tests
  ☆189Updated last year
• riscv-non-isa / riscv-toolchain-conventions
  Documenting the expected behaviour and supported command-line switches for GNU and LLVM based RISC-V toolchains
  ☆150Updated last week
• riscv / riscv-plic-spec
  PLIC Specification
  ☆150Updated 2 months ago
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆300Updated 2 years ago
• riscvarchive / riscv-CMOs
  ☆89Updated 2 months ago
• RoaLogic / RV12
  RISC-V CPU Core
  ☆392Updated 4 months ago
• chipsalliance / Cores-VeeR-EH2
  ☆247Updated 2 years ago
• SpinalHDL / NaxRiscv
  ☆301Updated 2 weeks ago
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆304Updated 9 months ago
• rafaelcalcada / rvx
  RISC-V soft-core microcontroller for FPGA implementation
  ☆186Updated 3 weeks ago
• pulp-platform / cheshire
  A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
  ☆296Updated this week
• riscv-non-isa / riscv-iommu
  RISC-V IOMMU Specification
  ☆139Updated last week
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆164Updated 5 years ago
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆303Updated this week
• bucaps / marss-riscv
  TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems
  ☆161Updated 3 years ago
• pulp-platform / mempool
  A scalable 256/1024-RISC-V-core system with low-latency access into shared L1 memory.
  ☆310Updated this week
• riscv-software-src / riscof
  ☆93Updated 2 months ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆177Updated 6 months ago