scarv / xcrypto

Related projects ⓘ

Alternatives and complementary repositories for xcrypto

• mjosaarinen / lwaes_isa
  [HISTORICAL] A Lightweight (RISC-V) ISA Extension for AES and SM4
  ☆34Updated 3 years ago
• chipsalliance / caliptra-rtl
  HW Design Collateral for Caliptra RoT IP
  ☆75Updated this week
• ucb-bar / sha3
  ☆76Updated 8 months ago
• optimsoc / optimsoc
  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
  ☆80Updated 3 years ago
• hex-five / multizone-sdk
  MultiZone® Security TEE is the quick and safe way to add security and separation to any RISC-V processors. The RISC-V standard ISA doesn'…
  ☆82Updated 9 months ago
• rvkrypto / rvkrypto-fips
  [HISTORICAL] FIPS and higher-level algorithm tests for RISC-V Crypto Extension
  ☆26Updated 3 months ago
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆111Updated last month
• riscv / configuration-structure
  RISC-V Configuration Structure
  ☆37Updated 3 weeks ago
• firesim / firechip
  Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …
  ☆56Updated 4 years ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆161Updated 3 months ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆67Updated 6 months ago
• mit-ll / CEP
  The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freel…
  ☆60Updated last year
• siliconcompiler / zerosoc
  Demo SoC for SiliconCompiler.
  ☆52Updated 3 weeks ago
• microsoft / cheriot-ibex
  cheriot-ibex is a RTL implementation of CHERIoT ISA based on LowRISC's Ibex core.
  ☆78Updated 3 weeks ago
• chipsalliance / omnixtend
  OmniXtend cache coherence protocol
  ☆78Updated 4 years ago
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆78Updated 3 months ago
• secworks / cmac
  Implementation of the CMAC keyed hash function using AES as block cipher.
  ☆12Updated last year
• keystone-enclave / riscv-pk
  Security monitor for Keystone Enclave (mirror of riscv-pk). Will be deprecated when openSBI port is ready
  ☆36Updated 3 years ago
• chipsalliance / Cores-SweRV_fpga
  ☆39Updated 4 years ago
• westerndigitalcorporation / swerv_eh1_fpga
  FPGA reference design for the the Swerv EH1 Core
  ☆67Updated 4 years ago
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆77Updated 2 weeks ago
• mupq / pqriscv-vexriscv
  VexRiscv reference platforms for the pqriscv project
  ☆15Updated 8 months ago
• pulp-platform / bigpulp
  ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
  ☆50Updated 2 years ago
• stnolting / fpga_puf
  Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.
  ☆125Updated 2 years ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆63Updated 7 months ago
• ymherklotz / verismith
  Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
  ☆96Updated last week
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆115Updated last month
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆58Updated 2 months ago
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆85Updated 2 months ago
• CTSRD-CHERI / TestRIG
  Testing processors with Random Instruction Generation
  ☆29Updated last month