scarv / xcryptoLinks
XCrypto: a cryptographic ISE for RISC-V
☆92Updated 3 years ago
Alternatives and similar repositories for xcrypto
Users that are interested in xcrypto are comparing it to the libraries listed below
Sorting:
- [HISTORICAL] A Lightweight (RISC-V) ISA Extension for AES and SM4☆37Updated 4 years ago
- HW Design Collateral for Caliptra RoT IP☆124Updated last week
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆181Updated 8 months ago
- Implementation of the CMAC keyed hash function using AES as block cipher.☆16Updated 9 months ago
- [HISTORICAL] FIPS and higher-level algorithm tests for RISC-V Crypto Extension☆29Updated last year
- The SpinalHDL design of the Proteus core, an extensible RISC-V core.☆59Updated last week
- FPGA reference design for the the Swerv EH1 Core☆72Updated 6 years ago
- ☆29Updated 10 months ago
- RISC-V Configuration Structure☆41Updated last year
- Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.☆138Updated 3 years ago
- MultiZone® Security TEE is the quick and safe way to add security and separation to any RISC-V processors. The RISC-V standard ISA doesn'…☆87Updated last year
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Updated 6 years ago
- Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.☆136Updated 3 years ago
- Yet Another RISC-V Implementation☆99Updated last year
- Verilog implementation of the SHA-512 hash function.☆44Updated this week
- Security monitor for Keystone Enclave (mirror of riscv-pk). Will be deprecated when openSBI port is ready☆35Updated 4 years ago
- This repository contains the hardware design source files of the Hex Five X300 RISC-V SoC. The X300 is Hex Five's official reference HW p…☆32Updated last year
- VexRiscv reference platforms for the pqriscv project☆16Updated last year
- This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory prot…☆94Updated 2 weeks ago
- Mutation Cover with Yosys (MCY)☆89Updated this week
- SCARV: a side-channel hardened RISC-V platform☆28Updated 3 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 4 years ago
- OmniXtend cache coherence protocol☆82Updated 7 months ago
- An open-source custom cache generator.☆34Updated last year
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆153Updated last year
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆152Updated last week
- The multi-core cluster of a PULP system.☆111Updated last week
- SpinalHDL - Cryptography libraries☆58Updated last year
- True Random Number Generator core implemented in Verilog.☆78Updated 5 years ago
- cheriot-ibex is a RTL implementation of CHERIoT ISA based on LowRISC's Ibex core.☆117Updated 4 months ago