Alternatives and similar repositories for cv32e40x

Users that are interested in cv32e40x are comparing it to the libraries listed below

• openhwgroup / programs
  Documentation for the OpenHW Group's set of CORE-V RISC-V cores
  ☆219Updated 5 months ago
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆278Updated last month
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆150Updated last year
• rafaelcalcada / rvx
  RISC-V soft-core microcontroller for FPGA implementation
  ☆186Updated 3 weeks ago
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆235Updated 11 months ago
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆304Updated 9 months ago
• SpinalHDL / NaxRiscv
  ☆300Updated this week
• pulp-platform / cheshire
  A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
  ☆296Updated this week
• pulp-platform / mempool
  A scalable 256/1024-RISC-V-core system with low-latency access into shared L1 memory.
  ☆310Updated this week
• openhwgroup / core-v-mcu
  This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
  ☆187Updated last month
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆303Updated this week
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆300Updated 2 years ago
• chipsalliance / Cores-VeeR-EH2
  ☆247Updated 2 years ago
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆331Updated 11 months ago
• pulp-platform / register_interface
  Generic Register Interface (contains various adapters)
  ☆133Updated last month
• RoaLogic / RV12
  RISC-V CPU Core
  ☆393Updated 4 months ago
• riscv-non-isa / riscv-trace-spec
  RISC-V Processor Trace Specification
  ☆195Updated last month
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆122Updated 4 months ago
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆185Updated last week
• SpinalHDL / VexiiRiscv
  Like VexRiscv, but, Harder, Better, Faster, Stronger
  ☆190Updated this week
• IObundle / iob-soc
  RISC-V System on Chip Template
  ☆159Updated 2 months ago
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆273Updated last month
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆186Updated last month
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆218Updated 5 years ago
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆164Updated 5 years ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆177Updated 6 months ago
• pulp-platform / snitch
  ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!
  ☆226Updated last year
• riscv-ovpsim / imperas-riscv-tests
  ☆189Updated last year
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆539Updated 3 weeks ago
• chipsalliance / VeeR-ISS
  ☆150Updated 2 years ago