openhwgroup / cv32e40x
4 stage, in-order, compute RISC-V core based on the CV32E40P
☆226Updated 3 months ago
Alternatives and similar repositories for cv32e40x:
Users that are interested in cv32e40x are comparing it to the libraries listed below
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆140Updated 3 months ago
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆205Updated this week
- RISC-V Debug Support for our PULP RISC-V Cores☆241Updated 3 months ago
- VeeR EL2 Core☆263Updated this week
- CORE-V Family of RISC-V Cores☆228Updated this week
- Instruction Set Generator initially contributed by Futurewei☆271Updated last year
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆454Updated this week
- RISC-V 32-bit microcontroller developed in Verilog☆165Updated 3 months ago
- ☆275Updated this week
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆172Updated last year
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆223Updated this week
- Generic Register Interface (contains various adapters)☆106Updated 4 months ago
- FuseSoC-based SoC for VeeR EH1 and EL2☆306Updated 2 months ago
- Verilog Configurable Cache☆169Updated 2 months ago
- ☆225Updated 2 years ago
- A 256-RISC-V-core system with low-latency access into shared L1 memory.☆282Updated last week
- RISC-V RV64GC emulator designed for RTL co-simulation☆220Updated 2 months ago
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆204Updated 4 years ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆166Updated 6 months ago
- RISC-V System on Chip Template☆156Updated this week
- pulp_soc is the core building component of PULP based SoCs☆79Updated last week
- Like VexRiscv, but, Harder, Better, Faster, Stronger☆142Updated this week
- RISC-V CPU Core☆307Updated 8 months ago
- RISC-V Verification Interface☆84Updated 5 months ago
- A Fast, Low-Overhead On-chip Network☆165Updated this week
- Functional verification project for the CORE-V family of RISC-V cores.☆489Updated this week
- RiscyOO: RISC-V Out-of-Order Processor☆154Updated 4 years ago
- Tile based architecture designed for computing efficiency, scalability and generality☆243Updated this week
- Common SystemVerilog components☆570Updated last week
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆67Updated 10 months ago