openhwgroup / cv32e40xLinks
4 stage, in-order, compute RISC-V core based on the CV32E40P
☆240Updated 9 months ago
Alternatives and similar repositories for cv32e40x
Users that are interested in cv32e40x are comparing it to the libraries listed below
Sorting:
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆147Updated 9 months ago
- RISC-V Debug Support for our PULP RISC-V Cores☆265Updated 3 months ago
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆218Updated 2 months ago
- RISC-V RV64GC emulator designed for RTL co-simulation☆229Updated 8 months ago
- RISC-V microcontroller IP core developed in Verilog☆175Updated 3 months ago
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆272Updated this week
- CORE-V Family of RISC-V Cores☆283Updated 5 months ago
- A 256-RISC-V-core system with low-latency access into shared L1 memory.☆300Updated this week
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆184Updated 2 weeks ago
- ☆293Updated last month
- VeeR EL2 Core☆292Updated 2 weeks ago
- Instruction Set Generator initially contributed by Futurewei☆290Updated last year
- RISC-V CPU Core☆359Updated last month
- ☆240Updated 2 years ago
- FuseSoC-based SoC for VeeR EH1 and EL2☆321Updated 7 months ago
- Tile based architecture designed for computing efficiency, scalability and generality☆263Updated last month
- Generic Register Interface (contains various adapters)☆124Updated last month
- ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!☆226Updated last year
- Like VexRiscv, but, Harder, Better, Faster, Stronger☆168Updated last week
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆117Updated 3 weeks ago
- RISC-V System on Chip Template☆158Updated this week
- RiscyOO: RISC-V Out-of-Order Processor☆159Updated 5 years ago
- Verilog Configurable Cache☆180Updated 8 months ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆171Updated 3 weeks ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆178Updated 2 months ago
- RISC-V Processor Trace Specification☆191Updated this week
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆516Updated 5 months ago
- ☆141Updated last year
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆218Updated 4 years ago
- Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)☆272Updated last week