RISC-V Open Source Supervisor Binary Interface
☆1,407Mar 11, 2026Updated last week
Alternatives and similar repositories for opensbi
Users that are interested in opensbi are comparing it to the libraries listed below
Sorting:
- Documentation for the RISC-V Supervisor Binary Interface☆462Updated this week
- RISC-V Proxy Kernel☆687Oct 2, 2025Updated 5 months ago
- Spike, a RISC-V ISA Simulator☆3,034Feb 26, 2026Updated 3 weeks ago
- RISC-V Supervisor Binary Interface (RISC-V SBI) library in Rust; runs on M or HS mode; good support for embedded Rust ecosystem. For bina…☆1,257Updated this week
- GNU toolchain for RISC-V, including GCC☆4,409Mar 13, 2026Updated last week
- RISC-V Assembly Programmer's Manual☆1,620Updated this week
- PLIC Specification☆152Mar 14, 2026Updated last week
- RISC-V Instruction Set Manual☆4,529Mar 14, 2026Updated last week
- RISC-V Opcodes☆841Mar 14, 2026Updated last week
- ☆1,145Jan 22, 2026Updated last month
- Freedom U Software Development Kit (FUSDK)☆298Jan 23, 2026Updated last month
- A RISC-V ELF psABI Document☆836Mar 10, 2026Updated last week
- Fork of OpenOCD that has RISC-V support☆511Oct 9, 2025Updated 5 months ago
- "Das U-Boot" Source Tree☆4,977Mar 13, 2026Updated last week
- Linux KVM RISC-V repo☆62Mar 6, 2026Updated 2 weeks ago
- Rocket Chip Generator☆3,722Feb 25, 2026Updated 3 weeks ago
- RISC-V IOMMU Specification☆152Mar 14, 2026Updated last week
- ☆660Updated this week
- Keystone Enclave (QEMU + HiFive Unleashed)☆522Mar 10, 2025Updated last year
- Xv6 for RISC-V☆9,359Dec 17, 2025Updated 3 months ago
- Sail RISC-V model☆679Updated this week
- Super fast RISC-V ISA emulator for XiangShan processor☆314Mar 11, 2026Updated last week
- Documentation and status of UEFI on RISC-V☆64Aug 25, 2021Updated 4 years ago
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,105Mar 11, 2026Updated last week
- KVM RISC-V HowTOs☆47Jun 9, 2022Updated 3 years ago
- Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)☆289Updated this week
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,845Mar 10, 2026Updated last week
- RISC-V Architecture Profiles☆177Mar 13, 2026Updated last week
- ☆34Updated this week
- Working draft of the proposed RISC-V Bitmanipulation extension☆215Mar 20, 2024Updated 2 years ago
- OpenXuantie - OpenC910 Core☆1,397Jun 28, 2024Updated last year
- Working Draft of the RISC-V Debug Specification Standard☆507Updated this week
- OpenEmbedded/Yocto layer for RISC-V Architecture☆427Mar 3, 2026Updated 2 weeks ago
- RISC-V emulator for CLI and Web written in Rust with WebAssembly. It supports xv6 and Linux (ongoing).☆941May 29, 2024Updated last year
- Open-source high-performance RISC-V processor☆6,904Updated this week
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,063Feb 11, 2026Updated last month
- SiFive OpenEmbedded / Yocto BSP Layer☆55Jan 23, 2026Updated last month
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,183Updated this week
- Chisel: A Modern Hardware Design Language☆4,611Updated this week