RISC-V Open Source Supervisor Binary Interface
☆1,379Updated this week
Alternatives and similar repositories for opensbi
Users that are interested in opensbi are comparing it to the libraries listed below
Sorting:
- Documentation for the RISC-V Supervisor Binary Interface☆455Feb 6, 2026Updated 3 weeks ago
- RISC-V Proxy Kernel☆688Oct 2, 2025Updated 4 months ago
- Spike, a RISC-V ISA Simulator☆3,023Feb 13, 2026Updated 2 weeks ago
- RISC-V Supervisor Binary Interface (RISC-V SBI) library in Rust; runs on M or HS mode; good support for embedded Rust ecosystem. For bina…☆1,247Feb 10, 2026Updated 2 weeks ago
- GNU toolchain for RISC-V, including GCC☆4,368Feb 13, 2026Updated 2 weeks ago
- RISC-V Assembly Programmer's Manual☆1,612Updated this week
- RISC-V Instruction Set Manual☆4,500Feb 20, 2026Updated last week
- PLIC Specification☆151Feb 6, 2026Updated 3 weeks ago
- RISC-V Opcodes☆839Feb 21, 2026Updated last week
- ☆1,128Jan 22, 2026Updated last month
- A RISC-V ELF psABI Document☆831Feb 6, 2026Updated 3 weeks ago
- Freedom U Software Development Kit (FUSDK)☆296Jan 23, 2026Updated last month
- Fork of OpenOCD that has RISC-V support☆509Oct 9, 2025Updated 4 months ago
- Rocket Chip Generator☆3,696Updated this week
- ☆649Updated this week
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,079Feb 5, 2026Updated 3 weeks ago
- Sail RISC-V model☆671Updated this week
- "Das U-Boot" Source Tree☆4,952Updated this week
- Xv6 for RISC-V☆9,257Dec 17, 2025Updated 2 months ago
- Working Draft of the RISC-V Debug Specification Standard☆504Feb 5, 2026Updated 3 weeks ago
- Super fast RISC-V ISA emulator for XiangShan processor☆311Updated this week
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,817Feb 18, 2026Updated last week
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,026Feb 11, 2026Updated 2 weeks ago
- RISC-V emulator for CLI and Web written in Rust with WebAssembly. It supports xv6 and Linux (ongoing).☆939May 29, 2024Updated last year
- Documentation and status of UEFI on RISC-V☆64Aug 25, 2021Updated 4 years ago
- Working draft of the proposed RISC-V Bitmanipulation extension☆216Mar 20, 2024Updated last year
- RISC-V Architecture Profiles☆175Feb 18, 2026Updated last week
- Keystone Enclave (QEMU + HiFive Unleashed)☆521Mar 10, 2025Updated 11 months ago
- Linux KVM RISC-V repo☆62Updated this week
- Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)☆286Updated this week
- OpenXuantie - OpenC910 Core☆1,389Jun 28, 2024Updated last year
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,149Updated this week
- Chisel: A Modern Hardware Design Language☆4,588Updated this week
- Low level access to RISC-V processors☆1,067Feb 9, 2026Updated 2 weeks ago
- OpenEmbedded/Yocto layer for RISC-V Architecture☆425Feb 19, 2026Updated last week
- RISC-V IOMMU Specification☆147Updated this week
- Open-source high-performance RISC-V processor☆6,875Updated this week
- Verilator open-source SystemVerilog simulator and lint system☆3,381Updated this week
- RISC-V cryptography extensions standardisation work.☆403Mar 8, 2024Updated last year