rems-project / sail
Sail architecture definition language
β709Updated this week
Alternatives and similar repositories for sail:
Users that are interested in sail are comparing it to the libraries listed below
- Sail RISC-V modelβ524Updated last week
- Working Draft of the RISC-V J Extension Specificationβ184Updated last month
- A core language for rule-based hardware design π¦β148Updated 6 months ago
- Working draft of the proposed RISC-V Bitmanipulation extensionβ210Updated last year
- RISC-V Formal Verification Frameworkβ596Updated 3 years ago
- UCLID5: formal modeling, verification, and synthesis of computational systemsβ141Updated 3 weeks ago
- RISC-V simulator for x86-64β702Updated 3 years ago
- RISC-V support for LLVM projects (LLVM, Clang, ...)β266Updated 8 months ago
- Low Level Hardware Description β A foundation for building hardware design tools.β411Updated 2 years ago
- Bluespec Compiler (BSC)β996Updated last week
- Working Draft of the RISC-V Debug Specification Standardβ482Updated last month
- Konata is an instruction pipeline visualizer for Onikiri2-Kanata/Gem5-O3PipeView formats. You can download the pre-built binaries from htβ¦β443Updated last year
- RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performanceβ366Updated last year
- A Satisfiability Modulo Theories (SMT) solver for the theories of fixed-size bit-vectors, arrays and uninterpreted functions.β344Updated 7 months ago
- Tools to process ARM's Machine Readable Architecture Specificationβ126Updated 5 years ago
- A Platform for High-Level Parametric Hardware Specification and its Modular Verificationβ151Updated 6 months ago
- Intermediate Language (IL) for Hardware Accelerator Generatorsβ527Updated this week
- Fearless hardware designβ175Updated last week
- A Just-In-Time Compiler for Verilog from VMware Researchβ444Updated 3 years ago
- A formal semantics of the RISC-V ISA in Haskellβ163Updated last year
- Flexible Intermediate Representation for RTLβ740Updated 7 months ago
- Documenting the expected behaviour and supported command-line switches for GNU and LLVM based RISC-V toolchainsβ149Updated last week
- SymbiYosys (sby) -- Front-end for Yosys-based formal verification flowsβ441Updated last week
- Bitwuzla is a Satisfiability Modulo Theories (SMT) solver for the theories of fixed-size bit-vectors, floating-point arithmetic, arrays aβ¦β245Updated last week
- FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibilityβ919Updated 2 weeks ago
- RISC-V RV64GC emulator designed for RTL co-simulationβ224Updated 4 months ago
- RISC-V Proxy Kernelβ623Updated 2 weeks ago
- RISC-V Opcodesβ744Updated 3 weeks ago
- β150Updated last year
- RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)β322Updated 3 years ago