Sail architecture definition language
☆883May 20, 2026Updated this week
Alternatives and similar repositories for sail
Users that are interested in sail are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Sail RISC-V model☆705May 18, 2026Updated last week
- Sail version of Arm ISA definition, currently for Armv9.3-A, and with the previous Sail Armv8.5-A model☆94Apr 27, 2026Updated 3 weeks ago
- Symbolic execution tool for Sail ISA specifications☆89Feb 27, 2026Updated 2 months ago
- CHERI-RISC-V model written in Sail☆66Jul 10, 2025Updated 10 months ago
- A work-in-progress language and compiler for verified low-level programming☆331May 5, 2026Updated 3 weeks ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Lem semantic definition language☆157May 6, 2026Updated 2 weeks ago
- The Vellvm (Verified LLVM) coq development.☆474Updated this week
- Semantics of x86-64 in K☆171Mar 4, 2020Updated 6 years ago
- A Platform for High-Level Parametric Hardware Specification and its Modular Verification☆167May 4, 2026Updated 3 weeks ago
- Armv8 Native Code Symbolic Simulator in Lean☆102Nov 21, 2025Updated 6 months ago
- Crucible is a library for symbolic simulation of imperative programs☆767May 17, 2026Updated last week
- Verified Software Toolchain☆494Updated this week
- CakeML: A Verified Implementation of ML☆1,157Updated this week
- Bluespec Compiler (BSC)☆1,111May 15, 2026Updated last week
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- A core language for rule-based hardware design 🦑☆173Dec 10, 2025Updated 5 months ago
- Circuit IR Compilers and Tools☆2,129May 19, 2026Updated last week
- Creusot helps you prove your Rust code is correct.☆1,590Updated this week
- The CompCert formally-verified C compiler☆2,176Updated this week
- Example implementation of Arm's Architecture Specification Language (ASL)☆57Sep 14, 2025Updated 8 months ago
- The Ott tool for writing definitions of programming languages and calculi☆413Mar 10, 2026Updated 2 months ago
- Low Level Hardware Description — A foundation for building hardware design tools.☆434Apr 20, 2022Updated 4 years ago
- Semantic model for aspects of ELF static linking and DWARF debug information☆58Jul 20, 2025Updated 10 months ago
- Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)☆39Mar 30, 2021Updated 5 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Spike, a RISC-V ISA Simulator☆3,115Updated this week
- RISC-V Formal Verification Framework☆631Apr 6, 2022Updated 4 years ago
- Automatic verification of LLVM optimizations☆1,107Apr 27, 2026Updated 3 weeks ago
- A Library for Representing Recursive and Impure Programs in Coq☆250May 7, 2026Updated 2 weeks ago
- Formal Reasoning About Programs☆729Mar 23, 2026Updated 2 months ago
- CoreIR Symbolic Analyzer☆75Oct 27, 2020Updated 5 years ago
- Flexible Intermediate Representation for RTL☆750Aug 20, 2024Updated last year
- Type-checker for the λΠ-calculus modulo rewriting☆236Apr 26, 2026Updated last month
- egg is a flexible, high-performance e-graph library☆1,734Apr 14, 2026Updated last month
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- An executable specification of the RISCV ISA in L3.☆43Mar 1, 2019Updated 7 years ago
- Tools to process ARM's Machine Readable Architecture Specification☆137Jan 1, 2020Updated 6 years ago
- Embeddable Lambda Prolog Interpreter☆363Updated this week
- A fast RISC-V emulator based on the RISC-V Sail model, and an experimental ARM one☆88Apr 17, 2026Updated last month
- A formal semantics of the RISC-V ISA in Haskell☆175Aug 13, 2023Updated 2 years ago
- Tricks you wish the Coq manual told you [maintainer=@tchajed]☆548May 28, 2025Updated 11 months ago
- A minimal development of SSA theory☆237Apr 30, 2026Updated 3 weeks ago