Alternatives and similar repositories for sail

Users that are interested in sail are comparing it to the libraries listed below

• riscv / sail-riscv
  Sail RISC-V model
  ☆573Updated this week
• calyxir / calyx
  Intermediate Language (IL) for Hardware Accelerator Generators
  ☆539Updated this week
• riscv / riscv-j-extension
  Working Draft of the RISC-V J Extension Specification
  ☆188Updated 2 months ago
• mit-plv / koika
  A core language for rule-based hardware design 🦑
  ☆156Updated last month
• cucapra / filament
  Fearless hardware design
  ☆177Updated this week
• Boolector / boolector
  A Satisfiability Modulo Theories (SMT) solver for the theories of fixed-size bit-vectors, arrays and uninterpreted functions.
  ☆350Updated 10 months ago
• B-Lang-org / bsc
  Bluespec Compiler (BSC)
  ☆1,028Updated last week
• bitwuzla / bitwuzla
  Bitwuzla is a Satisfiability Modulo Theories (SMT) solver for the theories of fixed-size bit-vectors, floating-point arithmetic, arrays a…
  ☆262Updated this week
• uclid-org / uclid
  UCLID5: formal modeling, verification, and synthesis of computational systems
  ☆145Updated last week
• fabianschuiki / llhd
  Low Level Hardware Description — A foundation for building hardware design tools.
  ☆419Updated 3 years ago
• lowRISC / riscv-llvm
  RISC-V support for LLVM projects (LLVM, Clang, ...)
  ☆270Updated 11 months ago
• vellvm / vellvm
  The Vellvm (Verified LLVM) coq development.
  ☆437Updated last week
• michaeljclark / rv8
  RISC-V simulator for x86-64
  ☆706Updated 3 years ago
• riscv / riscv-bitmanip
  Working draft of the proposed RISC-V Bitmanipulation extension
  ☆211Updated last year
• SRI-CSL / yices2
  SRI Yices SMT Solver
  ☆415Updated this week
• cucapra / dahlia
  Time-sensitive affine types for predictable hardware generation
  ☆145Updated this week
• SymbioticEDA / riscv-formal
  RISC-V Formal Verification Framework
  ☆603Updated 3 years ago
• seL4 / l4v
  seL4 specification and proofs
  ☆552Updated this week
• vmware-archive / cascade
  A Just-In-Time Compiler for Verilog from VMware Research
  ☆445Updated 4 years ago
• riscv / riscv-opcodes
  RISC-V Opcodes
  ☆777Updated this week
• mit-plv / riscv-semantics
  A formal semantics of the RISC-V ISA in Haskell
  ☆167Updated last year
• bluespec / Flute
  RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance
  ☆373Updated last year
• mit-plv / bedrock2
  A work-in-progress language and compiler for verified low-level programming
  ☆309Updated last week
• chipsalliance / firrtl
  Flexible Intermediate Representation for RTL
  ☆747Updated 10 months ago
• mit-plv / kami
  A Platform for High-Level Parametric Hardware Specification and its Modular Verification
  ☆155Updated 2 weeks ago
• AliveToolkit / alive2
  Automatic verification of LLVM optimizations
  ☆935Updated 2 weeks ago
• andrescv / jupiter
  RISC-V Assembler and Runtime Simulator
  ☆432Updated last year
• riscv / riscv-debug-spec
  Working Draft of the RISC-V Debug Specification Standard
  ☆486Updated 2 months ago
• herd / herdtools7
  The Herd toolsuite to deal with .cat memory models (version 7.xx)
  ☆261Updated this week
• janestreet / hardcaml
  Hardcaml is an OCaml library for designing hardware.
  ☆801Updated last month