rems-project / sailLinks
Sail architecture definition language
β811Updated this week
Alternatives and similar repositories for sail
Users that are interested in sail are comparing it to the libraries listed below
Sorting:
- Sail RISC-V modelβ632Updated last week
- A core language for rule-based hardware design π¦β166Updated this week
- Intermediate Language (IL) for Hardware Accelerator Generatorsβ568Updated this week
- UCLID5: formal modeling, verification, and synthesis of computational systemsβ152Updated 5 months ago
- The Vellvm (Verified LLVM) coq development.β450Updated this week
- Bluespec Compiler (BSC)β1,066Updated 3 weeks ago
- RISC-V simulator for x86-64β717Updated 3 years ago
- Working Draft of the RISC-V J Extension Specificationβ191Updated last month
- Bitwuzla is a Satisfiability Modulo Theories (SMT) solver for the theories of fixed-size bit-vectors, floating-point arithmetic, arrays aβ¦β296Updated last week
- A Satisfiability Modulo Theories (SMT) solver for the theories of fixed-size bit-vectors, arrays and uninterpreted functions.β355Updated last year
- A Platform for High-Level Parametric Hardware Specification and its Modular Verificationβ162Updated 3 weeks ago
- seL4 specification and proofsβ581Updated this week
- Fearless hardware designβ183Updated 3 months ago
- A formal semantics of the RISC-V ISA in Haskellβ172Updated 2 years ago
- RISC-V support for LLVM projects (LLVM, Clang, ...)β273Updated last year
- SRI Yices SMT Solverβ437Updated 3 months ago
- Time-sensitive affine types for predictable hardware generationβ147Updated last month
- Low Level Hardware Description β A foundation for building hardware design tools.β424Updated 3 years ago
- RISC-V Formal Verification Frameworkβ619Updated 3 years ago
- Working draft of the proposed RISC-V Bitmanipulation extensionβ216Updated last year
- Automatic verification of LLVM optimizationsβ1,010Updated last week
- A work-in-progress language and compiler for verified low-level programmingβ321Updated 2 weeks ago
- The Herd toolsuite to deal with .cat memory models (version 7.xx)β284Updated this week
- RISC-V Opcodesβ816Updated last week
- Verified Software Toolchainβ480Updated 3 weeks ago
- Konata is an instruction pipeline visualizer for Onikiri2-Kanata/Gem5-O3PipeView formats. You can download the pre-built binaries from htβ¦β502Updated last year
- A Just-In-Time Compiler for Verilog from VMware Researchβ447Updated 4 years ago
- RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performanceβ374Updated 2 years ago
- Pono: A flexible and extensible SMT-based model checkerβ117Updated last week
- Formal specification and verification of hardware, especially for security and privacy.β128Updated 3 years ago