rems-project / sailLinks
Sail architecture definition language
☆793Updated this week
Alternatives and similar repositories for sail
Users that are interested in sail are comparing it to the libraries listed below
Sorting:
- Sail RISC-V model☆614Updated last week
- Intermediate Language (IL) for Hardware Accelerator Generators☆559Updated this week
- Bluespec Compiler (BSC)☆1,054Updated 3 weeks ago
- UCLID5: formal modeling, verification, and synthesis of computational systems☆150Updated 3 months ago
- A core language for rule-based hardware design 🦑☆162Updated last week
- Working Draft of the RISC-V J Extension Specification☆191Updated last week
- Bitwuzla is a Satisfiability Modulo Theories (SMT) solver for the theories of fixed-size bit-vectors, floating-point arithmetic, arrays a…☆282Updated last week
- RISC-V simulator for x86-64☆709Updated 3 years ago
- RISC-V support for LLVM projects (LLVM, Clang, ...)☆270Updated last year
- A Satisfiability Modulo Theories (SMT) solver for the theories of fixed-size bit-vectors, arrays and uninterpreted functions.☆352Updated last year
- The Vellvm (Verified LLVM) coq development.☆443Updated this week
- RISC-V Formal Verification Framework☆611Updated 3 years ago
- Low Level Hardware Description — A foundation for building hardware design tools.☆421Updated 3 years ago
- seL4 specification and proofs☆567Updated 2 weeks ago
- Konata is an instruction pipeline visualizer for Onikiri2-Kanata/Gem5-O3PipeView formats. You can download the pre-built binaries from ht…☆485Updated last year
- Working draft of the proposed RISC-V Bitmanipulation extension☆214Updated last year
- A formal semantics of the RISC-V ISA in Haskell☆170Updated 2 years ago
- Hardcaml is an OCaml library for designing hardware.☆849Updated 2 weeks ago
- The Herd toolsuite to deal with .cat memory models (version 7.xx)☆279Updated this week
- SRI Yices SMT Solver☆429Updated last month
- A Platform for High-Level Parametric Hardware Specification and its Modular Verification☆162Updated 2 weeks ago
- Time-sensitive affine types for predictable hardware generation☆145Updated last week
- Working Draft of the RISC-V Debug Specification Standard☆492Updated this week
- RISC-V Opcodes☆807Updated last week
- Fearless hardware design☆183Updated 2 months ago
- Pono: A flexible and extensible SMT-based model checker☆112Updated last week
- RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance☆374Updated 2 years ago
- A work-in-progress language and compiler for verified low-level programming☆314Updated 2 weeks ago
- RISC-V Proxy Kernel☆664Updated 3 weeks ago
- SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows☆475Updated 2 weeks ago