openhwgroup / cvfpuLinks
Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
☆497Updated 3 months ago
Alternatives and similar repositories for cvfpu
Users that are interested in cvfpu are comparing it to the libraries listed below
Sorting:
- Common SystemVerilog components☆623Updated this week
- Functional verification project for the CORE-V family of RISC-V cores.☆545Updated last week
- Instruction Set Generator initially contributed by Futurewei☆284Updated last year
- BaseJump STL: A Standard Template Library for SystemVerilog☆575Updated 2 weeks ago
- This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…☆426Updated 2 weeks ago
- VeeR EL2 Core☆278Updated last week
- RISC-V Debug Support for our PULP RISC-V Cores☆257Updated last month
- RISC-V CPU Core☆327Updated 11 months ago
- FuseSoC-based SoC for VeeR EH1 and EL2☆320Updated 5 months ago
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆429Updated last week
- Bus bridges and other odds and ends☆560Updated last month
- Test suite designed to check compliance with the SystemVerilog standard.☆324Updated this week
- SystemVerilog to Verilog conversion☆630Updated 2 weeks ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,286Updated last week
- ☆326Updated 8 months ago
- Tile based architecture designed for computing efficiency, scalability and generality☆257Updated 2 weeks ago
- Verilog Configurable Cache☆178Updated 6 months ago
- ☆238Updated 2 years ago
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆213Updated 4 years ago
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆263Updated this week
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆393Updated this week
- A Linux-capable RISC-V multicore for and by the world☆701Updated last month
- ☆287Updated 2 months ago
- CORE-V Family of RISC-V Cores☆269Updated 3 months ago
- The UVM written in Python☆429Updated last month
- A DDR3 memory controller in Verilog for various FPGAs☆467Updated 3 years ago
- A Fast, Low-Overhead On-chip Network☆207Updated this week
- Opensource DDR3 Controller☆333Updated this week
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆237Updated 6 months ago
- lowRISC Style Guides☆429Updated 8 months ago