Alternatives and similar repositories for cvfpu

Users that are interested in cvfpu are comparing it to the libraries listed below

• pulp-platform / common_cells
  Common SystemVerilog components
  ☆637Updated last week
• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆436Updated 2 months ago
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆593Updated last week
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆290Updated last year
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆569Updated 3 weeks ago
• pulp-platform / pulp
  This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…
  ☆505Updated 8 months ago
• pulp-platform / ara
  The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …
  ☆448Updated this week
• ucb-bar / berkeley-hardfloat
  ☆334Updated 10 months ago
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆292Updated last week
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆653Updated last month
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆718Updated 3 months ago
• RoaLogic / RV12
  RISC-V CPU Core
  ☆359Updated last month
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆180Updated 7 months ago
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆265Updated 3 months ago
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆321Updated 7 months ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆576Updated 3 months ago
• sld-columbia / esp
  Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
  ☆381Updated 3 weeks ago
• SpinalHDL / NaxRiscv
  ☆293Updated 3 weeks ago
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆283Updated 5 months ago
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆263Updated last month
• chipsalliance / Cores-VeeR-EH2
  ☆240Updated 2 years ago
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆721Updated last week
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆334Updated last week
• pulp-platform / cheshire
  A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
  ☆271Updated this week
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆357Updated last year
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆218Updated 4 years ago
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆240Updated 8 months ago
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,339Updated last week
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆272Updated 5 years ago
• Xilinx / RapidWright
  Build Customized FPGA Implementations for Vivado
  ☆330Updated this week