openhwgroup / cvfpu
Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
☆418Updated last month
Related projects: ⓘ
- Common SystemVerilog components☆494Updated this week
- Instruction Set Generator initially contributed by Futurewei☆255Updated 11 months ago
- Functional verification project for the CORE-V family of RISC-V cores.☆425Updated 2 weeks ago
- VeeR EL2 Core☆243Updated this week
- BaseJump STL: A Standard Template Library for SystemVerilog☆498Updated 2 weeks ago
- ☆285Updated last week
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆350Updated this week
- This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…☆376Updated last month
- SystemVerilog to Verilog conversion☆535Updated 2 weeks ago
- FuseSoC-based SoC for VeeR EH1 and EL2☆280Updated 3 weeks ago
- RISC-V CPU Core☆280Updated 3 months ago
- Test suite designed to check compliance with the SystemVerilog standard.☆284Updated this week
- Verilog Configurable Cache☆165Updated 3 weeks ago
- RISC-V Debug Support for our PULP RISC-V Cores☆213Updated last month
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆208Updated last month
- CORE-V Family of RISC-V Cores☆199Updated 7 months ago
- Tile based architecture designed for computing efficiency, scalability and generality☆225Updated this week
- Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy☆328Updated this week
- ☆211Updated last year
- Bus bridges and other odds and ends☆470Updated 8 months ago
- RISC-V RV64GC emulator designed for RTL co-simulation☆210Updated last week
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆353Updated this week
- A Linux-capable RISC-V multicore for and by the world☆597Updated 2 weeks ago
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆196Updated 4 years ago
- This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…☆438Updated 5 months ago
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆187Updated last week
- ☆257Updated 3 weeks ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,048Updated last month
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆253Updated this week
- A 256-RISC-V-core system with low-latency access into shared L1 memory.☆263Updated this week