Alternatives and similar repositories for riscv-CMOs

Users that are interested in riscv-CMOs are comparing it to the libraries listed below

• riscv / riscv-aia
  ☆96Updated 2 months ago
• riscvarchive / riscv-aclint
  ☆42Updated 3 years ago
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆71Updated last year
• zero-day-labs / riscv-iommu
  IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
  ☆106Updated last month
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆235Updated last year
• riscv-ovpsim / imperas-riscv-tests
  ☆189Updated last year
• riscv / riscv-test-env
  ☆50Updated last month
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆164Updated 5 years ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆178Updated 6 months ago
• riscvarchive / riscv-code-size-reduction
  ☆147Updated last year
• openhwgroup / cva6-sdk
  CVA6 SDK containing RISC-V tools and Buildroot
  ☆75Updated last month
• litmus-tests / litmus-tests-riscv
  RISC-V architecture concurrency model litmus tests
  ☆92Updated 5 months ago
• bucaps / marss-riscv
  TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems
  ☆162Updated 3 years ago
• riscv-non-isa / riscv-iommu
  RISC-V IOMMU Specification
  ☆141Updated last week
• riscv-non-isa / tg-nexus-trace
  RISC-V Nexus Trace TG documentation and reference code
  ☆55Updated 10 months ago
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆81Updated 8 months ago
• zero-day-labs / riscv-aia
  AIA IP compliant with the RISC-V AIA spec
  ☆45Updated 9 months ago
• ultraembedded / exactstep
  Instruction set simulator for RISC-V, MIPS and ARM-v6m
  ☆103Updated 4 years ago
• josecm / riscv-hyp-tests
  A bare-metal application to test specific features of the risc-v hypervisor extension
  ☆42Updated last year
• carrv / carrv.github.io
  Workshop on Computer Architecture Research with RISC-V (CARRV)
  ☆41Updated last year
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆109Updated 3 weeks ago
• riscv-non-isa / riscv-trace-spec
  RISC-V Processor Trace Specification
  ☆196Updated last month
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆202Updated last year
• riscvarchive / riscv-eabi-spec
  Proposal for new Embedded ABI (EABI) for use in embedded RISC-V systems.
  ☆27Updated 4 years ago
• riscv / riscv-profiles
  RISC-V Architecture Profiles
  ☆166Updated 2 weeks ago
• IObundle / iob-soc
  RISC-V System on Chip Template
  ☆159Updated 3 months ago
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆150Updated last year
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆186Updated last month
• chipsalliance / omnixtend
  OmniXtend cache coherence protocol
  ☆82Updated 5 months ago
• chipsalliance / rocket-tools
  Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)
  ☆59Updated 2 years ago