Alternatives and similar repositories for riscv-zicond

Users that are interested in riscv-zicond are comparing it to the libraries listed below

• pulp-platform / culsans
  Tightly-coupled cache coherence unit for CVA6 using the ACE protocol
  ☆31Updated last year
• riscv-non-isa / riscv-semihosting
  ☆30Updated 3 weeks ago
• tenstorrent / rv-core-dv-kit
  ☆25Updated 3 months ago
• riscv / riscv-aia
  ☆89Updated 2 months ago
• pulp-platform / clint
  RISC-V Core Local Interrupt Controller (CLINT)
  ☆26Updated last year
• zephray / RISu064
  Dual-issue RV64IM processor for fun & learning
  ☆60Updated last year
• riscv / riscv-CMOs
  ☆86Updated 3 years ago
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆108Updated this week
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆70Updated last year
• riscv / riscv-bfloat16
  ☆35Updated 10 months ago
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆57Updated 4 months ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆105Updated 2 weeks ago
• stnolting / neorv32-riscof
  ✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
  ☆34Updated this week
• pulp-platform / pulp-runtime
  Simple runtime for Pulp platforms
  ☆48Updated 2 weeks ago
• riscv-non-isa / riscv-iommu
  RISC-V IOMMU Specification
  ☆117Updated 2 weeks ago
• tomverbeure / gdbwave
  GDB server to debug CPU simulation waveform traces
  ☆44Updated 3 years ago
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆97Updated last week
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆67Updated last year
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆146Updated 7 months ago
• riscvarchive / riscv-aclint
  ☆42Updated 3 years ago
• riscv-non-isa / riscv-uefi
  ☆29Updated 3 years ago
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆55Updated last week
• freechipsproject / chisel-cheatsheet
  Chisel Cheatsheet
  ☆33Updated 2 years ago
• B-Lang-org / bdw
  BSC Development Workstation (BDW)
  ☆29Updated 6 months ago
• pulp-platform / redmule
  ☆61Updated this week
• olofk / subservient
  Small SERV-based SoC primarily for OpenMPW tapeout
  ☆42Updated 5 months ago
• OpenXiangShan / nexus-am
  ☆35Updated this week
• rivosinc / hammer
  Infrastructure to drive Spike (RISC-V ISA Simulator) in cosim mode. Hammer provides a C++ and Python interface to interact with Spike.
  ☆33Updated last year
• AI-Vector-Accelerator / ava-core
  A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)
  ☆34Updated 4 years ago
• CTSRD-CHERI / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆32Updated this week