riscvarchive / riscv-zicond
The ISA specification for the ZiCondOps extension.
☆19Updated 8 months ago
Related projects ⓘ
Alternatives and complementary repositories for riscv-zicond
- The multi-core cluster of a PULP system.☆56Updated last week
- ☆27Updated 2 weeks ago
- ☆30Updated 4 months ago
- Simple runtime for Pulp platforms☆36Updated last week
- GDB server to debug CPU simulation waveform traces☆41Updated 2 years ago
- RISC-V Core Local Interrupt Controller (CLINT)☆24Updated last year
- ☆32Updated 2 weeks ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆60Updated 5 months ago
- The specification for the FIRRTL language☆46Updated this week
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆34Updated 3 weeks ago
- Proposed RISC-V Composable Custom Extensions Specification☆67Updated 6 months ago
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆27Updated 6 months ago
- Heterogeneous Cluster Interconnect to bind special-purpose HW accelerators with general-purpose cluster cores☆12Updated 3 months ago
- A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow …☆73Updated this week
- 64-bit multicore Linux-capable RISC-V processor☆78Updated 2 months ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆63Updated 7 months ago
- ✔️Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.☆25Updated this week
- AXI Adapter(s) for RISC-V Atomic Operations☆58Updated 2 months ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆75Updated this week
- RISC-V IOMMU Specification☆96Updated this week
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆42Updated 3 weeks ago
- A SystemVerilog source file pickler.☆51Updated last month
- Naive Educational RISC V processor☆74Updated last month
- RISC-V Configuration Structure☆37Updated 3 weeks ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆135Updated last month
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆93Updated this week
- ☆52Updated 2 years ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆131Updated 3 weeks ago
- ☆65Updated last month
- pulp_soc is the core building component of PULP based SoCs☆78Updated 3 months ago