Alternatives and similar repositories for riscv-zicond

Users that are interested in riscv-zicond are comparing it to the libraries listed below

• riscv-non-isa / riscv-semihosting
  ☆30Updated 3 weeks ago
• tenstorrent / rv-core-dv-kit
  ☆25Updated 4 months ago
• riscv / riscv-CMOs
  ☆86Updated 3 years ago
• riscv / riscv-bfloat16
  ☆35Updated last year
• riscv / riscv-aia
  ☆89Updated 3 months ago
• pulp-platform / pulp-runtime
  Simple runtime for Pulp platforms
  ☆48Updated 3 weeks ago
• riscv-non-isa / riscv-iommu
  RISC-V IOMMU Specification
  ☆123Updated this week
• OpenXiangShan / nexus-am
  ☆35Updated last month
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆104Updated last week
• tomverbeure / gdbwave
  GDB server to debug CPU simulation waveform traces
  ☆44Updated 3 years ago
• pulp-platform / carfield
  A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow …
  ☆107Updated this week
• riscv-non-isa / riscv-uefi
  ☆29Updated 3 years ago
• riscvarchive / riscv-code-size-reduction
  ☆149Updated last year
• microsoft / cheriot-ibex
  cheriot-ibex is a RTL implementation of CHERIoT ISA based on LowRISC's Ibex core.
  ☆112Updated this week
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆146Updated 8 months ago
• chipsalliance / fasm
  FPGA Assembly (FASM) Parser and Generator
  ☆93Updated 2 years ago
• riscv-non-isa / riscv-trace-spec
  RISC-V Processor Trace Specification
  ☆187Updated 2 weeks ago
• pulp-platform / culsans
  Tightly-coupled cache coherence unit for CVA6 using the ACE protocol
  ☆36Updated last year
• RISCVtestbed / rvv-rollback
  Translate RISC-V Vector Assembly from v1.0 to v0.7
  ☆34Updated 10 months ago
• riscv-admin / riscv-ovpsim
  ☆62Updated 4 years ago
• stnolting / neorv32-riscof
  ✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
  ☆34Updated this week
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆62Updated 5 months ago
• riscv-software-src / riscof
  ☆83Updated 3 months ago
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆112Updated last week
• t-crest / patmos
  Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
  ☆144Updated last month
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆58Updated last week
• riscv-software-src / riscv-isac
  ☆33Updated 8 months ago
• OpenXiangShan / CoupledL2
  Open-source non-blocking L2 cache
  ☆43Updated last week
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆71Updated 2 weeks ago
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆158Updated 5 years ago