riscvarchive / riscv-zicondLinks
The ISA specification for the ZiCondOps extension.
☆19Updated last year
Alternatives and similar repositories for riscv-zicond
Users that are interested in riscv-zicond are comparing it to the libraries listed below
Sorting:
- ☆89Updated 3 years ago
- The multi-core cluster of a PULP system.☆105Updated this week
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆147Updated 9 months ago
- Simple runtime for Pulp platforms☆48Updated 2 weeks ago
- RISC-V IOMMU Specification☆126Updated last week
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆117Updated last month
- ☆92Updated last week
- 64-bit multicore Linux-capable RISC-V processor☆95Updated 3 months ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆113Updated last week
- A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow …☆109Updated 3 weeks ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Updated 4 years ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆178Updated 3 months ago
- ☆37Updated last year
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆73Updated last year
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆63Updated 6 months ago
- pulp_soc is the core building component of PULP based SoCs☆80Updated 5 months ago
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆37Updated last year
- ☆30Updated this week
- ☆85Updated 4 months ago
- ☆149Updated last year
- Proposal for new Embedded ABI (EABI) for use in embedded RISC-V systems.☆27Updated 4 years ago
- A RISC-V Core (RV32I) written in Chisel HDL☆103Updated 4 months ago
- FPGA tool performance profiling☆102Updated last year
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆184Updated 3 weeks ago
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated last month
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆218Updated 2 months ago
- RISC-V Processor Trace Specification☆191Updated last week
- Lipsi: Probably the Smallest Processor in the World☆86Updated last year
- ☆42Updated 9 months ago
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆241Updated 9 months ago