Alternatives and similar repositories for riscv-plic-spec

Users that are interested in riscv-plic-spec are comparing it to the libraries listed below

• riscv / riscv-fast-interrupt
  Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
  ☆274Updated this week
• riscv / riscv-aia
  ☆92Updated 3 weeks ago
• riscv-non-isa / riscv-iommu
  RISC-V IOMMU Specification
  ☆126Updated this week
• litmus-tests / litmus-tests-riscv
  RISC-V architecture concurrency model litmus tests
  ☆85Updated 2 months ago
• riscv-non-isa / riscv-trace-spec
  RISC-V Processor Trace Specification
  ☆192Updated 3 weeks ago
• riscvarchive / riscv-aclint
  ☆42Updated 3 years ago
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆197Updated last year
• riscv / riscv-CMOs
  ☆89Updated 3 years ago
• riscv / riscv-profiles
  RISC-V Architecture Profiles
  ☆163Updated 6 months ago
• riscv-non-isa / riscv-toolchain-conventions
  Documenting the expected behaviour and supported command-line switches for GNU and LLVM based RISC-V toolchains
  ☆153Updated 2 weeks ago
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆266Updated 4 months ago
• riscv-ovpsim / imperas-riscv-tests
  ☆182Updated last year
• riscvarchive / riscv-code-size-reduction
  ☆149Updated last year
• riscvarchive / riscv-platform-specs
  RISC-V Profiles and Platform Specification
  ☆114Updated last year
• poweihuang17 / Documentation_Spike
  Documentation for RISC-V Spike
  ☆102Updated 6 years ago
• bucaps / marss-riscv
  TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems
  ☆155Updated 3 years ago
• michaeljclark / riscv-probe
  Simple machine mode program to probe RISC-V control and status registers
  ☆123Updated 2 years ago
• riscv-software-src / riscof
  ☆86Updated 4 months ago
• riscv-non-isa / riscv-arch-test
  ☆583Updated last week
• zero-day-labs / riscv-aia
  AIA IP compliant with the RISC-V AIA spec
  ☆44Updated 6 months ago
• cnrv / fpga-rocket-chip
  Wrapper for Rocket-Chip on FPGAs
  ☆136Updated 2 years ago
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆70Updated last year
• riscv / riscv-p-spec
  RISC-V Packed SIMD Extension
  ☆150Updated last year
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆292Updated last year
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆230Updated 9 months ago
• riscv / riscv-bitmanip
  Working draft of the proposed RISC-V Bitmanipulation extension
  ☆214Updated last year
• openhwgroup / programs
  Documentation for the OpenHW Group's set of CORE-V RISC-V cores
  ☆218Updated 3 months ago
• riscv / riscv-debug-spec
  Working Draft of the RISC-V Debug Specification Standard
  ☆495Updated 3 weeks ago
• josecm / riscv-hyp-tests
  A bare-metal application to test specific features of the risc-v hypervisor extension
  ☆40Updated last year
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆217Updated 5 years ago