riscv / riscv-plic-specLinks
PLIC Specification
☆140Updated 2 years ago
Alternatives and similar repositories for riscv-plic-spec
Users that are interested in riscv-plic-spec are comparing it to the libraries listed below
Sorting:
- Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)☆268Updated this week
- RISC-V IOMMU Specification☆119Updated this week
- ☆89Updated 3 months ago
- ☆86Updated 3 years ago
- RISC-V architecture concurrency model litmus tests☆79Updated 3 weeks ago
- ☆42Updated 3 years ago
- ☆149Updated last year
- RISC-V Processor Trace Specification☆184Updated last week
- Documenting the expected behaviour and supported command-line switches for GNU and LLVM based RISC-V toolchains☆151Updated last week
- Setup scripts and files needed to compile CoreMark on RISC-V☆68Updated 11 months ago
- RISC-V Torture Test☆196Updated 11 months ago
- ☆83Updated 2 months ago
- Instruction Set Generator initially contributed by Futurewei☆288Updated last year
- RISC-V Debug Support for our PULP RISC-V Cores☆258Updated 2 months ago
- ☆179Updated last year
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆237Updated 7 months ago
- RISC-V Architecture Profiles☆153Updated 4 months ago
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆214Updated last month
- Documentation for RISC-V Spike☆100Updated 6 years ago
- TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems☆153Updated 3 years ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆146Updated 7 months ago
- Simple machine mode program to probe RISC-V control and status registers☆121Updated 2 years ago
- ☆567Updated this week
- Working draft of the proposed RISC-V Bitmanipulation extension☆211Updated last year
- RISC-V Packed SIMD Extension☆148Updated last year
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆214Updated 4 years ago
- OpenXuantie - OpenC906 Core☆357Updated 11 months ago
- Wrapper for Rocket-Chip on FPGAs☆134Updated 2 years ago
- RISC-V RV64GC emulator designed for RTL co-simulation☆230Updated 7 months ago
- ☆289Updated 3 months ago