cliffordwolf / bextdepLinks
Reference Hardware Implementations of Bit Extract/Deposit Instructions
☆25Updated 8 years ago
Alternatives and similar repositories for bextdep
Users that are interested in bextdep are comparing it to the libraries listed below
Sorting:
- firrtlator is a FIRRTL C++ library☆23Updated 8 years ago
- Rigel is a language for describing image processing hardware embedded in Lua. Rigel can compile to Verilog hardware designs for Xilinx FP…☆56Updated 5 years ago
- An executable specification of the RISCV ISA in L3.☆42Updated 6 years ago
- The BERI and CHERI processor and hardware platform☆50Updated 8 years ago
- ☆30Updated 3 years ago
- Reticle evaluation (PLDI 2021)☆12Updated 4 years ago
- RISC-V RV64IS-compatible processor for the Kestrel-3☆21Updated 2 years ago
- A Verilog Synthesis Regression Test☆37Updated last year
- Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)☆38Updated 4 years ago
- Open source fpga project leveraging vtr CAD flow.☆26Updated 2 years ago
- Languages, Tools, and Techniques for Accelerator Design☆33Updated 4 years ago
- A Verilog parser for Haskell.☆36Updated 4 years ago
- A reconfigurable and extensible VLIW processor implemented in VHDL☆37Updated 10 years ago
- Verilog AST☆21Updated 2 years ago
- RISC-V port to Parallella Board☆13Updated 9 years ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆150Updated 3 weeks ago
- Manythread RISC-V overlay for FPGA clusters☆38Updated 2 months ago
- TestFloat release 3☆70Updated 9 months ago
- A multicore microprocessor test harness for measuring interference☆14Updated 5 years ago
- netlistDB - Intermediate format for digital hardware representation with graph database API☆32Updated 4 years ago
- A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code. (Results)☆40Updated 2 months ago
- ABC: System for Sequential Logic Synthesis and Formal Verification☆30Updated last week
- Original RISC-V 1.0 implementation. Not supported.☆42Updated 7 years ago
- Chisel library for Unum Type-III Posit Arithmetic☆45Updated 8 months ago
- The PE for the second generation CGRA (garnet).☆17Updated 7 months ago
- A place to share libraries and utilities that don't belong in the core bsc repo☆37Updated last month
- Verilog FPGA Parts Library. Old Octavo soft-CPU project.☆75Updated 6 years ago
- A powerful and modern open-source architecture description language.☆45Updated 8 years ago
- Formal semantics of BSV (Bluespec SystemVerilog), given as a Haskell Program and accompanying document☆18Updated 9 years ago
- Linear algebra accelerators for RISC-V (published in ICCD 17)☆67Updated 8 years ago