cliffordwolf / bextdep
Reference Hardware Implementations of Bit Extract/Deposit Instructions
☆24Updated 7 years ago
Alternatives and similar repositories for bextdep:
Users that are interested in bextdep are comparing it to the libraries listed below
- firrtlator is a FIRRTL C++ library☆21Updated 8 years ago
- A reconfigurable and extensible VLIW processor implemented in VHDL☆32Updated 10 years ago
- A Verilog Synthesis Regression Test☆37Updated last year
- Languages, Tools, and Techniques for Accelerator Design☆33Updated 3 years ago
- netlistDB - Intermediate format for digital hardware representation with graph database API☆31Updated 4 years ago
- Open source fpga project leveraging vtr CAD flow.☆26Updated 2 years ago
- Rigel is a language for describing image processing hardware embedded in Lua. Rigel can compile to Verilog hardware designs for Xilinx FP…☆56Updated 4 years ago
- An executable specification of the RISCV ISA in L3.☆42Updated 6 years ago
- An advanced header-only exact synthesis library☆25Updated 2 years ago
- ☆25Updated 2 years ago
- A Verilog parser for Haskell.☆34Updated 3 years ago
- RISC-V RV64IS-compatible processor for the Kestrel-3☆21Updated 2 years ago
- Open Processor Architecture☆26Updated 9 years ago
- A formal spec of the RISC-V Instruction Set Architecture, written in Bluespec BSV (executable, synthesizable)☆20Updated 7 years ago
- Polyhedral Compilation tool for High Level Synthesis.☆10Updated 10 years ago
- Reticle evaluation (PLDI 2021)☆12Updated 4 years ago
- A place to share libraries and utilities that don't belong in the core bsc repo☆35Updated last month
- Verilog AST☆21Updated last year
- Formal semantics of BSV (Bluespec SystemVerilog), given as a Haskell Program and accompanying document☆18Updated 8 years ago
- Chisel library for Unum Type-III Posit Arithmetic☆38Updated last month
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆33Updated 8 years ago
- The 3rd Iteration of the Berkeley RISC-V DMA Accelerator☆27Updated 5 years ago
- RISC-V GPGPU☆34Updated 5 years ago
- Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)☆36Updated 4 years ago
- Iodine: Verifying Constant-Time Execution of Hardware☆12Updated 4 years ago
- The BERI and CHERI processor and hardware platform☆50Updated 8 years ago
- RISC-V port to Parallella Board☆12Updated 8 years ago
- A time-predictable processor for mixed-criticality systems☆58Updated 6 months ago
- Original RISC-V 1.0 implementation. Not supported.☆41Updated 6 years ago
- L3 based MIPS specification and emulator☆15Updated 3 years ago