riscv-collab/riscv-openocd external links

---

GitHub - View repository

GitHub.dev - Open in online code editor

Star history - Growth chart over time

deps.dev - Dependencies and security vulnerabilities

Gitingest - Export source code for LLM usage

Repomix - Export source code for LLM usage

uithub - Export source code for LLM usage

Close

riscv-collab/riscv-openocd

Readme badge preview -

If you own this repo, copy the snippet below and add it to your README.md

---

Copy

[![RelatedRepos](https://img.shields.io/badge/related-repos-yellow)](https://relatedrepos.com/gh/riscv-collab/riscv-openocd)

Close

riscv-collab / riscv-openocdView on GitHubMore

• External links
• Readme badge

Fork of OpenOCD that has RISC-V support

☆512Oct 9, 2025Updated 5 months ago

Alternatives and similar repositories for riscv-openocd

Users that are interested in riscv-openocd are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.

• riscv / riscv-debug-spec

  View on GitHub
  Working Draft of the RISC-V Debug Specification Standard
  ☆507Mar 14, 2026Updated 2 weeks ago
• pulp-platform / riscv-dbg

  View on GitHub
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆303Feb 4, 2026Updated last month
• riscv-software-src / riscv-pk

  View on GitHub
  RISC-V Proxy Kernel
  ☆689Oct 2, 2025Updated 5 months ago
• riscv-software-src / riscv-isa-sim

  View on GitHub
  Spike, a RISC-V ISA Simulator
  ☆3,047Updated this week
• riscv-collab / riscv-gnu-toolchain

  View on GitHub
  GNU toolchain for RISC-V, including GCC
  ☆4,416Updated this week
• Simple, predictable pricing with DigitalOcean hosting • Ad
  Always know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
• riscvarchive / riscv-binutils-gdb

  View on GitHub
  RISC-V backports for binutils-gdb. Development is done upstream at the FSF.
  ☆151Jul 7, 2022Updated 3 years ago
• riscv / riscv-fast-interrupt

  View on GitHub
  Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
  ☆290Mar 20, 2026Updated last week
• riscvarchive / riscv-gcc

  View on GitHub
  ☆373May 22, 2023Updated 2 years ago
• riscvarchive / riscv-newlib

  View on GitHub
  RISC-V port of newlib
  ☆102Mar 15, 2022Updated 4 years ago
• riscv-software-src / riscv-tests

  View on GitHub
  ☆1,147Updated this week
• riscv-software-src / opensbi

  View on GitHub
  RISC-V Open Source Supervisor Binary Interface
  ☆1,418Mar 22, 2026Updated last week
• riscv / riscv-test-env

  View on GitHub
  ☆51Jan 9, 2026Updated 2 months ago
• riscv-boom / riscv-coremark

  View on GitHub
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆74Jul 19, 2024Updated last year
• openhwgroup / cva6

  View on GitHub
  The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…
  ☆2,861Updated this week
• DigitalOcean Gradient AI Platform • Ad
  Build production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
• riscvarchive / riscv-code-size-reduction

  View on GitHub
  ☆148Feb 29, 2024Updated 2 years ago
• riscvarchive / riscv-dejagnu

  View on GitHub
  DejaGnu RISC-V port
  ☆14May 23, 2022Updated 3 years ago
• riscv / riscv-isa-manual

  View on GitHub
  RISC-V Instruction Set Manual
  ☆4,549Updated this week
• riscv / riscv-arch-test

  View on GitHub
  ☆665Updated this week
• openocd-org / openocd

  View on GitHub
  Official OpenOCD Read-Only Mirror (no pull requests)
  ☆2,137Mar 8, 2026Updated 3 weeks ago
• riscvarchive / riscv-fesvr

  View on GitHub
  RISC-V Frontend Server
  ☆64Mar 31, 2019Updated 6 years ago
• riscv / riscv-opcodes

  View on GitHub
  RISC-V Opcodes
  ☆842Updated this week
• riscv-software-src / riscv-tools

  View on GitHub
  RISC-V Tools (ISA Simulator and Tests)
  ☆1,184Dec 22, 2022Updated 3 years ago
• chipsalliance / rocket-chip

  View on GitHub
  Rocket Chip Generator
  ☆3,730Feb 25, 2026Updated last month
• End-to-end encrypted email - Proton Mail • Ad
  Special offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
• riscv / riscv-bitmanip

  View on GitHub
  Working draft of the proposed RISC-V Bitmanipulation extension
  ☆215Mar 20, 2024Updated 2 years ago
• riscv-non-isa / riscv-trace-spec

  View on GitHub
  RISC-V Processor Trace Specification
  ☆211Updated this week
• openhwgroup / cv32e40p

  View on GitHub
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,203May 26, 2025Updated 10 months ago
• openhwgroup / core-v-verif

  View on GitHub
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆666Mar 8, 2026Updated 3 weeks ago
• syntacore / scr1

  View on GitHub
  SCR1 is a high-quality open-source RISC-V MCU core in Verilog
  ☆973Nov 15, 2024Updated last year
• SpinalHDL / VexRiscv

  View on GitHub
  A FPGA friendly 32 bit RISC-V CPU implementation
  ☆3,090Feb 11, 2026Updated last month
• riscv / riscv-crypto

  View on GitHub
  RISC-V cryptography extensions standardisation work.
  ☆408Mar 7, 2026Updated 3 weeks ago
• chipsalliance / VeeRwolf

  View on GitHub
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆338Dec 11, 2024Updated last year
• openhwgroup / programs

  View on GitHub
  Documentation for the OpenHW Group's set of CORE-V RISC-V cores
  ☆224Jan 11, 2026Updated 2 months ago
• Managed Kubernetes at scale on DigitalOcean • Ad
  DigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
• openhwgroup / cv32e40x

  View on GitHub
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆264Nov 6, 2024Updated last year
• pulp-platform / pulpissimo

  View on GitHub
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆466May 15, 2025Updated 10 months ago
• pulp-platform / jtag_dpi

  View on GitHub
  JTAG DPI module for SystemVerilog RTL simulations
  ☆32Oct 30, 2015Updated 10 years ago
• sergeykhbr / riscv_vhdl

  View on GitHub
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆685Jul 16, 2025Updated 8 months ago
• riscv-mcu / riscv-openocd

  View on GitHub
  Fork of OpenOCD that has RISC-V microcontroller support
  ☆35Nov 6, 2025Updated 4 months ago
• lowRISC / ibex

  View on GitHub
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,814Feb 17, 2026Updated last month
• chipsalliance / treadle

  View on GitHub
  Chisel/Firrtl execution engine
  ☆156Aug 21, 2024Updated last year