Alternatives and similar repositories for riscv-openocd

Users that are interested in riscv-openocd are comparing it to the libraries listed below

• riscv / riscv-debug-spec
  Working Draft of the RISC-V Debug Specification Standard
  ☆487Updated last month
• riscv-non-isa / riscv-arch-test
  ☆567Updated this week
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,080Updated 3 weeks ago
• riscvarchive / riscv-gcc
  ☆369Updated 2 years ago
• riscvarchive / riscv-software-list
  The RISC-V software tools list, as seen on riscv.org
  ☆466Updated 4 years ago
• syntacore / scr1
  SCR1 is a high-quality open-source RISC-V MCU core in Verilog
  ☆918Updated 7 months ago
• riscvarchive / riscv-cores-list
  RISC-V Cores, SoC platforms and SoCs
  ☆887Updated 4 years ago
• XUANTIE-RV / openc906
  OpenXuantie - OpenC906 Core
  ☆357Updated 11 months ago
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆883Updated 2 years ago
• riscv-software-src / riscv-pk
  RISC-V Proxy Kernel
  ☆639Updated last month
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆667Updated 3 weeks ago
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆258Updated 2 months ago
• litex-hub / linux-on-litex-vexriscv
  Linux on LiteX-VexRiscv
  ☆642Updated 2 weeks ago
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,568Updated last week
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆320Updated 6 months ago
• riscv / riscv-fast-interrupt
  Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
  ☆268Updated this week
• sifiveinc / freedom-u-sdk
  Freedom U Software Development Kit (FUSDK)
  ☆290Updated last month
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,135Updated 2 weeks ago
• pulp-platform / pulp
  This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…
  ☆497Updated 6 months ago
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆1,036Updated 3 years ago
• riscv / riscv-plic-spec
  PLIC Specification
  ☆140Updated 2 years ago
• riscv-software-src / riscv-tests
  ☆1,022Updated last week
• ucb-bar / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆715Updated 3 months ago
• riscv-non-isa / riscv-trace-spec
  RISC-V Processor Trace Specification
  ☆184Updated this week
• openrisc / mor1kx
  mor1kx - an OpenRISC 1000 processor IP core
  ☆545Updated 2 months ago
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆286Updated 2 weeks ago
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆559Updated 2 weeks ago
• RoaLogic / RV12
  RISC-V CPU Core
  ☆337Updated last week
• chipsalliance / Cores-VeeR-EH2
  ☆238Updated 2 years ago
• eugene-tarassov / vivado-risc-v
  Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
  ☆966Updated last week