Fork of OpenOCD that has RISC-V support
☆517Jul 17, 2026Updated last month
Alternatives and similar repositories for riscv-openocd
Users that are interested in riscv-openocd are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- RISC-V Debug Specification Standard☆528Aug 26, 2026Updated last week
- RISC-V Debug Support for our PULP RISC-V Cores☆324Updated this week
- Open Source Software for Developing on the Freedom E Platform - Deprecated☆583Jul 1, 2024Updated 2 years ago
- RISC-V Proxy Kernel☆708Oct 2, 2025Updated 11 months ago
- Spike, a RISC-V ISA Simulator☆3,220Updated this week
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- GNU toolchain for RISC-V, including GCC☆4,601Aug 27, 2026Updated last week
- RISC-V backports for binutils-gdb. Development is done upstream at the FSF.☆152Jul 7, 2022Updated 4 years ago
- ☆368May 22, 2023Updated 3 years ago
- Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)☆300Updated this week
- RISC-V port of newlib☆106Mar 15, 2022Updated 4 years ago
- ☆1,239Aug 14, 2026Updated 3 weeks ago
- RISC-V Open Source Supervisor Binary Interface☆1,530Updated this week
- ☆54Jan 9, 2026Updated 7 months ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆75Jul 19, 2024Updated 2 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆3,093Updated this week
- Common RTL blocks used in SiFive's projects☆194May 13, 2022Updated 4 years ago
- DejaGnu RISC-V port☆14May 23, 2022Updated 4 years ago
- ☆145Feb 29, 2024Updated 2 years ago
- RISC-V Instruction Set Manual☆4,806Updated this week
- Official OpenOCD Read-Only Mirror (no pull requests)☆2,311Updated this week
- The RISC-V Architectural Certification Tests (ACTs) are a set of assembly language tests designed to certify that a design faithfully imp…☆784Updated this week
- Rocket Chip Generator☆3,854Jun 2, 2026Updated 3 months ago
- RISC-V Frontend Server☆65Mar 31, 2019Updated 7 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- RISC-V Opcodes☆872Aug 24, 2026Updated 2 weeks ago
- RISC-V Tools (ISA Simulator and Tests)☆1,194Dec 22, 2022Updated 3 years ago
- Working draft of the proposed RISC-V Bitmanipulation extension☆219Mar 20, 2024Updated 2 years ago
- RISC-V Processor Trace Specification☆222Updated this week
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,285Aug 26, 2026Updated last week
- Functional verification project for the CORE-V family of RISC-V cores.☆717Aug 13, 2026Updated 3 weeks ago
- RISC-V cryptography extensions standardisation work.☆411Mar 7, 2026Updated 6 months ago
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆1,000Nov 15, 2024Updated last year
- FuseSoC-based SoC for VeeR EH1 and EL2☆343Dec 11, 2024Updated last year
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,243Aug 31, 2026Updated last week
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆230Jan 11, 2026Updated 7 months ago
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆278Nov 6, 2024Updated last year
- This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…☆495May 8, 2026Updated 3 months ago
- JTAG DPI module for SystemVerilog RTL simulations☆32Oct 30, 2015Updated 10 years ago
- Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators☆696Jul 16, 2025Updated last year
- Fork of OpenOCD that has RISC-V microcontroller support☆39Nov 6, 2025Updated 10 months ago