riscv-collab/riscv-openocd external links

---

GitHub - View repository

GitHub.dev - Open in online code editor

Star history - Growth chart over time

deps.dev - Dependencies and security vulnerabilities

Gitingest - Export source code for LLM usage

Repomix - Export source code for LLM usage

uithub - Export source code for LLM usage

Close

riscv-collab/riscv-openocd

Readme badge preview -

If you own this repo, copy the snippet below and add it to your README.md

---

Copy

[![RelatedRepos](https://img.shields.io/badge/related-repos-yellow)](https://relatedrepos.com/gh/riscv-collab/riscv-openocd)

Close

riscv-collab / riscv-openocdView on GitHubMore

• External links
• Readme badge

Fork of OpenOCD that has RISC-V support

☆511Oct 9, 2025Updated 5 months ago

Alternatives and similar repositories for riscv-openocd

Users that are interested in riscv-openocd are comparing it to the libraries listed below

• riscv / riscv-debug-spec

  View on GitHub
  Working Draft of the RISC-V Debug Specification Standard
  ☆505Mar 1, 2026Updated last week
• pulp-platform / riscv-dbg

  View on GitHub
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆297Feb 4, 2026Updated last month
• riscv-software-src / riscv-pk

  View on GitHub
  RISC-V Proxy Kernel
  ☆687Oct 2, 2025Updated 5 months ago
• riscvarchive / riscv-gcc

  View on GitHub
  ☆373May 22, 2023Updated 2 years ago
• riscv-software-src / riscv-isa-sim

  View on GitHub
  Spike, a RISC-V ISA Simulator
  ☆3,028Feb 26, 2026Updated last week
• riscv-collab / riscv-gnu-toolchain

  View on GitHub
  GNU toolchain for RISC-V, including GCC
  ☆4,386Feb 13, 2026Updated 3 weeks ago
• riscvarchive / riscv-binutils-gdb

  View on GitHub
  RISC-V backports for binutils-gdb. Development is done upstream at the FSF.
  ☆151Jul 7, 2022Updated 3 years ago
• riscv / riscv-fast-interrupt

  View on GitHub
  Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
  ☆287Feb 27, 2026Updated last week
• riscvarchive / riscv-dejagnu

  View on GitHub
  DejaGnu RISC-V port
  ☆14May 23, 2022Updated 3 years ago
• riscv-software-src / riscv-tests

  View on GitHub
  ☆1,133Jan 22, 2026Updated last month
• riscvarchive / riscv-code-size-reduction

  View on GitHub
  ☆148Feb 29, 2024Updated 2 years ago
• riscvarchive / riscv-newlib

  View on GitHub
  RISC-V port of newlib
  ☆102Mar 15, 2022Updated 3 years ago
• riscv-software-src / opensbi

  View on GitHub
  RISC-V Open Source Supervisor Binary Interface
  ☆1,387Feb 25, 2026Updated last week
• riscv / riscv-test-env

  View on GitHub
  ☆51Jan 9, 2026Updated 2 months ago
• openhwgroup / cva6

  View on GitHub
  The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…
  ☆2,828Feb 25, 2026Updated last week
• riscv / riscv-opcodes

  View on GitHub
  RISC-V Opcodes
  ☆842Updated this week
• riscv / riscv-arch-test

  View on GitHub
  ☆652Updated this week
• SpinalHDL / VexRiscv

  View on GitHub
  A FPGA friendly 32 bit RISC-V CPU implementation
  ☆3,032Feb 11, 2026Updated 3 weeks ago
• openhwgroup / core-v-verif

  View on GitHub
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆659Updated this week
• riscv-software-src / riscv-tools

  View on GitHub
  RISC-V Tools (ISA Simulator and Tests)
  ☆1,178Dec 22, 2022Updated 3 years ago
• openhwgroup / programs

  View on GitHub
  Documentation for the OpenHW Group's set of CORE-V RISC-V cores
  ☆225Jan 11, 2026Updated last month
• riscv / riscv-isa-manual

  View on GitHub
  RISC-V Instruction Set Manual
  ☆4,521Updated this week
• syntacore / scr1

  View on GitHub
  SCR1 is a high-quality open-source RISC-V MCU core in Verilog
  ☆964Nov 15, 2024Updated last year
• riscv / riscv-bitmanip

  View on GitHub
  Working draft of the proposed RISC-V Bitmanipulation extension
  ☆216Mar 20, 2024Updated last year
• openhwgroup / cv32e40p

  View on GitHub
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,190May 26, 2025Updated 9 months ago
• openocd-org / openocd

  View on GitHub
  Official OpenOCD Read-Only Mirror (no pull requests)
  ☆2,111Updated this week
• riscv-boom / riscv-coremark

  View on GitHub
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆73Jul 19, 2024Updated last year
• openhwgroup / cv32e40x

  View on GitHub
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆259Nov 6, 2024Updated last year
• riscv / riscv-crypto

  View on GitHub
  RISC-V cryptography extensions standardisation work.
  ☆406Updated this week
• riscv / meta-riscv

  View on GitHub
  OpenEmbedded/Yocto layer for RISC-V Architecture
  ☆425Feb 19, 2026Updated 2 weeks ago
• chipsalliance / rocket-chip

  View on GitHub
  Rocket Chip Generator
  ☆3,705Feb 25, 2026Updated last week
• riscv-mcu / riscv-openocd

  View on GitHub
  Fork of OpenOCD that has RISC-V microcontroller support
  ☆35Nov 6, 2025Updated 4 months ago
• sergeykhbr / riscv_vhdl

  View on GitHub
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆684Jul 16, 2025Updated 7 months ago
• chipsalliance / Cores-VeeR-EL2

  View on GitHub
  VeeR EL2 Core
  ☆321Updated this week
• riscv-non-isa / riscv-toolchain-conventions

  View on GitHub
  Documenting the expected behaviour and supported command-line switches for GNU and LLVM based RISC-V toolchains
  ☆151Feb 27, 2026Updated last week
• riscvarchive / riscv-CMOs

  View on GitHub
  ☆89Aug 26, 2025Updated 6 months ago
• pulp-platform / pulpissimo

  View on GitHub
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆461May 15, 2025Updated 9 months ago
• lowRISC / ibex

  View on GitHub
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,785Feb 17, 2026Updated 2 weeks ago
• riscv / riscv-plic-spec

  View on GitHub
  PLIC Specification
  ☆151Feb 6, 2026Updated last month