riscv / riscv-cfiLinks
This specification is integrated into the Priv. and Unpriv. specifications. This repo is no longer maintained. Please refer to the Priv. and Unpriv. specifications at https://github.com/riscv/riscv-isa-manual
☆87Updated this week
Alternatives and similar repositories for riscv-cfi
Users that are interested in riscv-cfi are comparing it to the libraries listed below
Sorting:
- RISC-V Security Model☆30Updated this week
- This specification will define the RISC-V privilege ISA extensions required to support Supervisor Domain isolation for multi-tenant secur…☆52Updated this week
- Artifacts for Cascade: CPU Fuzzing via Intricate Program Generation (USENIX Security 2024)☆128Updated 9 months ago
- RISC-V IOMMU Specification☆119Updated last week
- ☆149Updated last year
- Documenting the expected behaviour and supported command-line switches for GNU and LLVM based RISC-V toolchains☆151Updated 2 weeks ago
- This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usag…☆21Updated 4 months ago
- Proof-of-concept implementation for the paper "A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs" (IEEE S&P 2023)☆68Updated 3 months ago
- ☆86Updated 3 years ago
- Risc-V hypervisor for TEE development☆117Updated last week
- CHERI-RISC-V model written in Sail☆59Updated last week
- A bare-metal application to test specific features of the risc-v hypervisor extension☆40Updated last year
- IOMMU IP compliant with the RISC-V IOMMU Specification v1.0☆95Updated 2 months ago
- Proof of concepts for speculative attacks using the BOOM core (https://github.com/riscv-boom/riscv-boom)☆64Updated 5 years ago
- RISC-V Architecture Profiles☆151Updated 4 months ago
- rfuzz: coverage-directed fuzzing for RTL research platform☆105Updated 3 years ago
- ☆89Updated 3 months ago
- Rust RISC-V Virtual Machine☆104Updated 7 months ago
- RISC-V Processor Trace Specification☆184Updated this week
- Documentation of the RISC-V C API☆76Updated this week
- ☆30Updated this week
- Machine-readable database of the RISC-V specification, and tools to generate various views☆75Updated this week
- RISC-V architecture concurrency model litmus tests☆79Updated 3 weeks ago
- This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory prot…☆72Updated this week
- Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)☆268Updated this week
- The repo contains the SPMP architectural specification, which includes capabilities like access control of read/write/execute requests by…☆16Updated last month
- PLIC Specification☆140Updated 2 years ago
- A libgloss replacement for RISC-V that supports HTIF☆38Updated last year
- RISC-V Disassembler with support for RV32/RV64/RV128 IMAFDC☆100Updated 2 years ago
- A port of the RIPE suite to RISC-V.☆29Updated 6 years ago