riscv/riscv-cfi external links

---

GitHub - View repository

GitHub.dev - Open in online code editor

Star history - Growth chart over time

deps.dev - Dependencies and security vulnerabilities

Gitingest - Export source code for LLM usage

Repomix - Export source code for LLM usage

uithub - Export source code for LLM usage

Close

riscv/riscv-cfi

Readme badge preview -

If you own this repo, copy the snippet below and add it to your README.md

---

Copy

[![RelatedRepos](https://img.shields.io/badge/related-repos-yellow)](https://relatedrepos.com/gh/riscv/riscv-cfi)

Close

riscv / riscv-cfiView on GitHubMore

• External links
• Readme badge

This specification is integrated into the Priv. and Unpriv. specifications. This repo is no longer maintained. Please refer to the Priv. and Unpriv. specifications at https://github.com/riscv/riscv-isa-manual

☆95Apr 3, 2026Updated 2 weeks ago

Alternatives and similar repositories for riscv-cfi

Users that are interested in riscv-cfi are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.

• riscv / riscv-memory-tagging

  View on GitHub
  Memory Tagging ISA extension that can be used by software to enforce memory tag checks on memory loads and stores
  ☆31Mar 29, 2026Updated 2 weeks ago
• riscv / riscv-smmtt

  View on GitHub
  This specification will define the RISC-V privilege ISA extensions required to support Supervisor Domain isolation for multi-tenant secur…
  ☆68Apr 7, 2026Updated last week
• riscv / riscv-security-model

  View on GitHub
  RISC-V Security Model
  ☆34Apr 2, 2026Updated 2 weeks ago
• riscv / riscv-bfloat16

  View on GitHub
  ☆38Mar 6, 2026Updated last month
• riscv / riscv-control-transfer-records

  View on GitHub
  This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usag…
  ☆23Mar 10, 2026Updated last month
• GPU virtual machines on DigitalOcean Gradient AI • Ad
  Get to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
• jwnhy / coffer

  View on GitHub
  Coffer is a RISC-V trusted execution environment developed in Rust.
  ☆20Mar 3, 2022Updated 4 years ago
• riscv-non-isa / riscv-iommu

  View on GitHub
  RISC-V IOMMU Specification
  ☆157Apr 2, 2026Updated 2 weeks ago
• riscvarchive / riscv-zicond

  View on GitHub
  The ISA specification for the ZiCondOps extension.
  ☆19Mar 21, 2024Updated 2 years ago
• rivosinc / salus

  View on GitHub
  Risc-V hypervisor for TEE development
  ☆133Jan 14, 2026Updated 3 months ago
• riscv / riscv-j-extension

  View on GitHub
  Working Draft of the RISC-V J Extension Specification
  ☆194Mar 6, 2026Updated last month
• riscv-non-isa / riscv-external-debug-security

  View on GitHub
  The RISC-V External Debug Security Specification
  ☆20Apr 6, 2026Updated last week
• riscvarchive / security

  View on GitHub
  RISC-V Security HC admin repo
  ☆17Jan 7, 2025Updated last year
• riscv / riscv-fast-interrupt

  View on GitHub
  Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
  ☆290Apr 7, 2026Updated last week
• riscv-non-isa / riscv-semihosting

  View on GitHub
  ☆32Apr 8, 2026Updated last week
• 1-Click AI Models by DigitalOcean Gradient • Ad
  Deploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
• riscvarchive / riscv-tee

  View on GitHub
  ☆38Aug 6, 2022Updated 3 years ago
• riscvarchive / riscv-CMOs

  View on GitHub
  ☆89Aug 26, 2025Updated 7 months ago
• riscv-non-isa / riscv-uefi

  View on GitHub
  ☆34Apr 8, 2026Updated last week
• openhwgroup / cv32e40x-dv

  View on GitHub
  CV32E40X Design-Verification environment
  ☆16Mar 25, 2024Updated 2 years ago
• riscv-non-isa / riscv-brs

  View on GitHub
  The Boot and Runtime Services (BRS) specification provides the software requirements for system vendors and Operating System Vendors (OSV…
  ☆58Apr 8, 2026Updated last week
• dramforever / opensbi-h

  View on GitHub
  [No longer active] A fork of OpenSBI, with software-emulated hypervisor extension support
  ☆43Aug 15, 2025Updated 8 months ago
• zzyppo / tagged_security_riscv

  View on GitHub
  Implementation of Tagged Memory security policies into Rocket Core
  ☆10Nov 8, 2016Updated 9 years ago
• riscv-non-isa / riscv-server-platform

  View on GitHub
  The RISC-V Server Platform specification defines a standardized set of hardware and sofware capabilities, that portable system software, …
  ☆26Mar 10, 2026Updated last month
• riscv-non-isa / riscv-trace-spec

  View on GitHub
  RISC-V Processor Trace Specification
  ☆216Updated this week
• Managed hosting for WordPress and PHP on Cloudways • Ad
  Managed hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
• Smilencelsy / Control-Flow-Integrity

  View on GitHub
  Sth in Control-Flow Integrity
  ☆20Dec 25, 2018Updated 7 years ago
• bu-icsg / PHMon

  View on GitHub
  This repository contains the hardware, software, and OS support for the Programmable Hardware Monitor (PHMon).
  ☆28Aug 10, 2020Updated 5 years ago
• uCFI-GATech / ucfi-compiler

  View on GitHub
  ☆17Sep 20, 2019Updated 6 years ago
• riscv-non-isa / riscv-sbi-doc

  View on GitHub
  Documentation for the RISC-V Supervisor Binary Interface
  ☆468Apr 7, 2026Updated last week
• draperlaboratory / hope-RIPE

  View on GitHub
  A port of the RIPE suite to RISC-V.
  ☆29Oct 10, 2018Updated 7 years ago
• riscvarchive / riscv-code-size-reduction

  View on GitHub
  ☆148Feb 29, 2024Updated 2 years ago
• CircuitCoder / ChannelOS

  View on GitHub
  What if everything is a io_uring?
  ☆17Nov 10, 2022Updated 3 years ago
• rivosinc / cove

  View on GitHub
  RISC-V Confidential VM Extension
  ☆15Jan 14, 2026Updated 3 months ago
• riscv-non-isa / riscv-c-api-doc

  View on GitHub
  Documentation of the RISC-V C API
  ☆84Apr 9, 2026Updated last week
• GPU virtual machines on DigitalOcean Gradient AI • Ad
  Get to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
• riscvarchive / configuration-structure

  View on GitHub
  RISC-V Configuration Structure
  ☆41Oct 30, 2024Updated last year
• riscv-non-isa / riscv-ap-tee

  View on GitHub
  This repo holds the work area and revisions of the non-ISA specification created by the RISC-V AP-TEE TG. This specification defines the …
  ☆67Mar 7, 2026Updated last month
• riscv / riscv-p-spec

  View on GitHub
  RISC-V Packed SIMD Extension
  ☆165Apr 1, 2026Updated 2 weeks ago
• cnrv / OSEDA

  View on GitHub
  Open-Source EDA workshop for RISC-V community
  ☆12Jul 27, 2022Updated 3 years ago
• SoftwareLanguagesSecurityLab / ConFIRM

  View on GitHub
  ☆25Jun 16, 2021Updated 4 years ago
• riscv-admin / trusted-computing

  View on GitHub
  ☆23Jun 23, 2023Updated 2 years ago
• riscv / riscv-opcodes

  View on GitHub
  RISC-V Opcodes
  ☆853Mar 24, 2026Updated 3 weeks ago