riscv / riscv-cfiLinks
This specification is integrated into the Priv. and Unpriv. specifications. This repo is no longer maintained. Please refer to the Priv. and Unpriv. specifications at https://github.com/riscv/riscv-isa-manual
☆92Updated this week
Alternatives and similar repositories for riscv-cfi
Users that are interested in riscv-cfi are comparing it to the libraries listed below
Sorting:
- RISC-V Security Model☆33Updated last week
- This specification will define the RISC-V privilege ISA extensions required to support Supervisor Domain isolation for multi-tenant secur…☆63Updated last week
- Artifacts for Cascade: CPU Fuzzing via Intricate Program Generation (USENIX Security 2024)☆137Updated last year
- Risc-V hypervisor for TEE development☆125Updated 4 months ago
- rfuzz: coverage-directed fuzzing for RTL research platform☆112Updated 3 years ago
- Proof-of-concept implementation for the paper "A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs" (IEEE S&P 2023)☆73Updated 7 months ago
- RISC-V IOMMU Specification☆139Updated this week
- CHERI-RISC-V model written in Sail☆65Updated 4 months ago
- Working Draft of the RISC-V J Extension Specification☆191Updated 3 weeks ago
- RISC-V Architecture Profiles☆166Updated this week
- Proof of concepts for speculative attacks using the BOOM core (https://github.com/riscv-boom/riscv-boom)☆66Updated 6 years ago
- This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usag…☆23Updated 8 months ago
- This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory prot…☆85Updated this week
- Documenting the expected behaviour and supported command-line switches for GNU and LLVM based RISC-V toolchains☆150Updated this week
- Documentation of the RISC-V C API☆77Updated last week
- Rust RISC-V Virtual Machine☆110Updated 2 months ago
- ☆89Updated 2 months ago
- ☆147Updated last year
- RISC-V Processor Trace Specification☆195Updated last month
- Monorepo containing a machine-readable database of the RISC-V specification and artifact generation tools☆113Updated this week
- ☆39Updated 4 years ago
- A bare-metal application to test specific features of the risc-v hypervisor extension☆42Updated last year
- ☆96Updated 2 months ago
- IOMMU IP compliant with the RISC-V IOMMU Specification v1.0☆106Updated last month
- ☆33Updated 3 years ago
- Using Data Memory-Dependent Prefetchers to Leak Data at Rest☆38Updated 3 years ago
- TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems☆161Updated 3 years ago
- This repo holds the work area and revisions of the non-ISA specification created by the RISC-V AP-TEE TG. This specification defines the …☆62Updated 5 months ago
- RISC-V architecture concurrency model litmus tests☆91Updated 5 months ago
- Testing processors with Random Instruction Generation☆48Updated last month