☆99Mar 6, 2026Updated this week
Alternatives and similar repositories for riscv-aia
Users that are interested in riscv-aia are comparing it to the libraries listed below
Sorting:
- AIA IP compliant with the RISC-V AIA spec☆46Jan 27, 2025Updated last year
- RISC-V IOMMU Specification☆148Updated this week
- ☆42Jan 14, 2022Updated 4 years ago
- PLIC Specification☆151Feb 6, 2026Updated last month
- RISC-V Architecture Profiles☆177Updated this week
- ☆34Feb 6, 2026Updated last month
- ☆38Jul 9, 2024Updated last year
- Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)☆287Feb 27, 2026Updated last week
- The ISA specification for the ZiCondOps extension.☆19Mar 21, 2024Updated last year
- ☆89Aug 26, 2025Updated 6 months ago
- hypocaust-2, a type-1 hypervisor with H extension run on RISC-V machine☆59Nov 30, 2023Updated 2 years ago
- RISC-V Processor Trace Specification☆208Feb 27, 2026Updated last week
- This specification will define the RISC-V privilege ISA extensions required to support Supervisor Domain isolation for multi-tenant secur…☆66Feb 27, 2026Updated last week
- The RAS Error-record Register Interface provides a specification to augment RAS features in RISC-V SOC hardware to standardize reporting …☆11Mar 1, 2026Updated last week
- The repo holds the draft non-ISA Server SoC specification being developed by the Server SoC specification TG and to release intermediate …☆30Feb 26, 2026Updated last week
- Main Repo for the OpenHW Group Software Task Group☆17Mar 11, 2025Updated 11 months ago
- User-mode trap-and-emulate hypervisor for RISC-V☆14Feb 11, 2022Updated 4 years ago
- ☆148Feb 29, 2024Updated 2 years ago
- hypercraft is a VMM library written in Rust.☆54Oct 20, 2024Updated last year
- RISC-V Core Local Interrupt Controller (CLINT)☆30Feb 14, 2026Updated 3 weeks ago
- Documentation for the RISC-V Supervisor Binary Interface☆456Updated this week
- ☆18Jul 26, 2024Updated last year
- Bootloader recovery and updater tool for StarFive JH71x0 SoCs.☆15Apr 30, 2022Updated 3 years ago
- ☆19Oct 13, 2025Updated 4 months ago
- This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usag…☆23Updated this week
- Coffer is a RISC-V trusted execution environment developed in Rust.☆20Mar 3, 2022Updated 4 years ago
- hypocaust, a S-mode trap and emulate type-1 hypervisor run on RISC-V machine.☆49Feb 20, 2023Updated 3 years ago
- This repo holds the work area and revisions of the non-ISA specification created by the RISC-V AP-TEE TG. This specification defines the …☆66Dec 18, 2025Updated 2 months ago
- ☆39Sep 15, 2021Updated 4 years ago
- My RV64 CPU (Work in progress)☆19Dec 22, 2022Updated 3 years ago
- Linux kernel source tree☆21Updated this week
- RISC-V architecture concurrency model litmus tests☆100Jan 21, 2026Updated last month
- Working Draft of the RISC-V Debug Specification Standard☆505Mar 1, 2026Updated last week
- Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.☆39Feb 6, 2024Updated 2 years ago
- Documenting the expected behaviour and supported command-line switches for GNU and LLVM based RISC-V toolchains☆151Feb 27, 2026Updated last week
- Linux KVM RISC-V repo☆62Updated this week
- A matrix extension proposal for AI applications under RISC-V architecture☆164Feb 11, 2025Updated last year
- [No longer active] A fork of OpenSBI, with software-emulated hypervisor extension support☆42Aug 15, 2025Updated 6 months ago
- Framework for writing tests for RISC-V CPU/SOC validation.☆11Jan 19, 2026Updated last month