openhwgroup / programsLinks
Documentation for the OpenHW Group's set of CORE-V RISC-V cores
☆218Updated 3 months ago
Alternatives and similar repositories for programs
Users that are interested in programs are comparing it to the libraries listed below
Sorting:
- RISC-V Debug Support for our PULP RISC-V Cores☆270Updated 4 months ago
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆244Updated 10 months ago
- VeeR EL2 Core☆297Updated 2 weeks ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆150Updated 10 months ago
- CORE-V Family of RISC-V Cores☆293Updated 6 months ago
- RISC-V Processor Trace Specification☆193Updated last month
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆187Updated last month
- RISC-V RV64GC emulator designed for RTL co-simulation☆230Updated 9 months ago
- Instruction Set Generator initially contributed by Futurewei☆293Updated last year
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆282Updated this week
- ☆244Updated 2 years ago
- Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)☆277Updated last week
- RISC-V microcontroller IP core developed in Verilog☆179Updated 4 months ago
- RISC-V CPU Core☆373Updated 2 months ago
- ☆295Updated last month
- FuseSoC-based SoC for VeeR EH1 and EL2☆324Updated 9 months ago
- RISC-V Torture Test☆196Updated last year
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆119Updated 2 months ago
- ☆187Updated last year
- A 256-RISC-V-core system with low-latency access into shared L1 memory.☆304Updated last week
- RISC-V System on Chip Template☆159Updated 3 weeks ago
- Tile based architecture designed for computing efficiency, scalability and generality☆265Updated 2 weeks ago
- Ariane is a 6-stage RISC-V CPU☆144Updated 5 years ago
- ☆145Updated last year
- The multi-core cluster of a PULP system.☆108Updated last week
- RISC-V Verification Interface☆102Updated 3 months ago
- Generic Register Interface (contains various adapters)☆128Updated last month
- CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…☆406Updated last week
- ☆147Updated last year
- ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!☆226Updated last year