openhwgroup / programs

Related projects ⓘ

Alternatives and complementary repositories for programs

• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆212Updated this week
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆252Updated this week
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆224Updated 2 months ago
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆129Updated last week
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆264Updated last year
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆206Updated 8 months ago
• openhwgroup / core-v-mcu
  This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
  ☆168Updated 9 months ago
• chipsalliance / Cores-VeeR-EH2
  ☆214Updated last year
• riscv-steel / riscv-steel
  RISC-V 32-bit microcontroller developed in Verilog
  ☆156Updated 2 weeks ago
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆215Updated last month
• riscv-non-isa / riscv-trace-spec
  RISC-V Processor Trace Specification
  ☆162Updated last week
• riscv / riscv-fast-interrupt
  Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
  ☆245Updated last month
• SpinalHDL / NaxRiscv
  ☆269Updated last month
• pulp-platform / cheshire
  A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
  ☆194Updated this week
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆433Updated 2 weeks ago
• pulp-platform / mempool
  A 256-RISC-V-core system with low-latency access into shared L1 memory.
  ☆275Updated this week
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆444Updated this week
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆229Updated last week
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆167Updated 2 months ago
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆287Updated 2 months ago
• RoaLogic / RV12
  RISC-V CPU Core
  ☆287Updated 5 months ago
• IObundle / iob-soc
  RISC-V System on Chip Template
  ☆153Updated this week
• chipsalliance / VeeR-ISS
  ☆121Updated last year
• sifive / sifive-blocks
  Common RTL blocks used in SiFive's projects
  ☆179Updated 2 years ago
• SpinalHDL / SaxonSoc
  SoC based on VexRiscv and ICE40 UP5K
  ☆151Updated 7 months ago
• openhwgroup / cvw
  CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…
  ☆265Updated this week
• riscv-ovpsim / imperas-riscv-tests
  ☆160Updated 10 months ago
• pulp-platform / register_interface
  Generic Register Interface (contains various adapters)
  ☆99Updated last month
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆513Updated this week
• ucb-bar / testchipip
  ☆80Updated 3 weeks ago