openhwgroup / programsLinks
Documentation for the OpenHW Group's set of CORE-V RISC-V cores
☆223Updated last month
Alternatives and similar repositories for programs
Users that are interested in programs are comparing it to the libraries listed below
Sorting:
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆252Updated last year
- RISC-V Debug Support for our PULP RISC-V Cores☆288Updated 2 weeks ago
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆194Updated 3 weeks ago
- VeeR EL2 Core☆310Updated last week
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆153Updated last year
- RISC-V Processor Trace Specification☆199Updated 2 weeks ago
- CORE-V Family of RISC-V Cores☆314Updated 10 months ago
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆313Updated 2 weeks ago
- Instruction Set Generator initially contributed by Futurewei☆304Updated 2 years ago
- ☆253Updated 3 years ago
- RISC-V RV64GC emulator designed for RTL co-simulation☆237Updated last year
- Open-source RISC-V microcontroller for embedded and FPGA applications☆189Updated this week
- Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)☆283Updated this week
- ☆301Updated last month
- FuseSoC-based SoC for VeeR EH1 and EL2☆336Updated last year
- RISC-V CPU Core☆403Updated 6 months ago
- A scalable 256/1024-RISC-V-core system with low-latency access into shared L1 memory.☆313Updated this week
- RISC-V Torture Test☆206Updated last year
- Generic Register Interface (contains various adapters)☆134Updated last month
- ☆191Updated 2 years ago
- Tile based architecture designed for computing efficiency, scalability and generality☆276Updated 3 months ago
- RISC-V System on Chip Template☆159Updated 4 months ago
- ☆150Updated 2 years ago
- The multi-core cluster of a PULP system.☆110Updated 2 months ago
- CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…☆457Updated this week
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆189Updated 3 months ago
- RISC-V Verification Interface☆134Updated 3 weeks ago
- Ariane is a 6-stage RISC-V CPU☆151Updated 6 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆124Updated 5 months ago
- A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow …☆116Updated 5 months ago