Alternatives and similar repositories for programs

Users that are interested in programs are comparing it to the libraries listed below

• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆245Updated 10 months ago
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆273Updated last week
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆150Updated 11 months ago
• openhwgroup / core-v-mcu
  This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
  ☆187Updated 2 months ago
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆297Updated this week
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆299Updated 7 months ago
• pulp-platform / cheshire
  A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
  ☆286Updated this week
• chipsalliance / Cores-VeeR-EH2
  ☆244Updated 2 years ago
• riscv / riscv-fast-interrupt
  Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
  ☆277Updated this week
• riscv-non-isa / riscv-trace-spec
  RISC-V Processor Trace Specification
  ☆194Updated last month
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆295Updated last year
• RoaLogic / RV12
  RISC-V CPU Core
  ☆387Updated 3 months ago
• rafaelcalcada / rvx
  RISC-V microcontroller IP core developed in Verilog
  ☆183Updated 5 months ago
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆230Updated 10 months ago
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆324Updated 9 months ago
• pulp-platform / mempool
  A 256-RISC-V-core system with low-latency access into shared L1 memory.
  ☆306Updated this week
• IObundle / iob-soc
  RISC-V System on Chip Template
  ☆159Updated last month
• SpinalHDL / NaxRiscv
  ☆296Updated last week
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆108Updated 2 weeks ago
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆266Updated last week
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆532Updated last month
• chipsalliance / VeeR-ISS
  ☆145Updated last year
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆197Updated last year
• riscv-ovpsim / imperas-riscv-tests
  ☆189Updated last year
• pulp-platform / snitch
  ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!
  ☆227Updated last year
• openhwgroup / cvw
  CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…
  ☆415Updated 2 weeks ago
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆103Updated this week
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆599Updated last week
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆183Updated last week
• pulp-platform / register_interface
  Generic Register Interface (contains various adapters)
  ☆130Updated last month