openhwgroup / programsLinks
Documentation for the OpenHW Group's set of CORE-V RISC-V cores
☆214Updated last month
Alternatives and similar repositories for programs
Users that are interested in programs are comparing it to the libraries listed below
Sorting:
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆237Updated 7 months ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆146Updated 7 months ago
- VeeR EL2 Core☆286Updated 2 weeks ago
- RISC-V Debug Support for our PULP RISC-V Cores☆258Updated 2 months ago
- RISC-V RV64GC emulator designed for RTL co-simulation☆230Updated 7 months ago
- CORE-V Family of RISC-V Cores☆274Updated 4 months ago
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆177Updated this week
- RISC-V CPU Core☆337Updated last week
- RISC-V microcontroller IP core developed in Verilog☆174Updated 2 months ago
- RISC-V Processor Trace Specification☆184Updated this week
- Instruction Set Generator initially contributed by Futurewei☆288Updated last year
- ☆238Updated 2 years ago
- ☆289Updated 3 months ago
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆267Updated this week
- The multi-core cluster of a PULP system.☆101Updated this week
- Verilog Configurable Cache☆178Updated 6 months ago
- ☆137Updated last year
- FuseSoC-based SoC for VeeR EH1 and EL2☆320Updated 6 months ago
- Tile based architecture designed for computing efficiency, scalability and generality☆261Updated this week
- RISC-V Torture Test☆196Updated 11 months ago
- ☆179Updated last year
- Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)☆268Updated this week
- Generic Register Interface (contains various adapters)☆121Updated last week
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆504Updated 4 months ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆175Updated last month
- Functional verification project for the CORE-V family of RISC-V cores.☆559Updated 2 weeks ago
- RISC-V System on Chip Template☆158Updated this week
- RISC-V Verification Interface☆94Updated 3 weeks ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆165Updated this week
- A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow …☆106Updated last week