RISC-V Debug Support for our PULP RISC-V Cores
☆324Aug 25, 2026Updated last week
Alternatives and similar repositories for riscv-dbg
Users that are interested in riscv-dbg are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Generic Register Interface (contains various adapters)☆141Aug 6, 2026Updated 3 weeks ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,282Aug 26, 2026Updated last week
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆230Jan 11, 2026Updated 7 months ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆160Oct 31, 2024Updated last year
- The multi-core cluster of a PULP system.☆116Aug 4, 2026Updated 3 weeks ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆278Nov 6, 2024Updated last year
- Fork of OpenOCD that has RISC-V support☆517Jul 17, 2026Updated last month
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆236Updated this week
- Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)☆299Aug 26, 2026Updated last week
- Common SystemVerilog components☆792Aug 21, 2026Updated last week
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆98Aug 20, 2026Updated last week
- Functional verification project for the CORE-V family of RISC-V cores.☆715Aug 13, 2026Updated 2 weeks ago
- RISC-V Debug Specification Standard☆528Aug 26, 2026Updated last week
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,677Updated this week
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- FuseSoC-based SoC for VeeR EH1 and EL2☆343Dec 11, 2024Updated last year
- Instruction Set Generator initially contributed by Futurewei☆313Oct 17, 2023Updated 2 years ago
- This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…☆493May 8, 2026Updated 3 months ago
- RISC-V CPU Core☆445Jun 24, 2025Updated last year
- CORE-V Family of RISC-V Cores☆370Mar 31, 2026Updated 5 months ago
- A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow …☆127Aug 26, 2026Updated last week
- Ibex is a small 32-bit RISC-V CPU core with high-level of verification (previously known as zero-riscy)☆2,033Updated this week
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆632Jul 24, 2026Updated last month
- RISC-V Processor Tracing tools and library☆16Mar 17, 2024Updated 2 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- VeeR EH2 core☆276Jul 20, 2026Updated last month
- VeeR EL2 Core☆345Updated this week
- VeeR EH1 core☆966Jul 16, 2026Updated last month
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆3,090Updated this week
- RSD: RISC-V Out-of-Order Superscalar Processor☆1,196Aug 18, 2026Updated 2 weeks ago
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆365Updated this week
- IOPMP IP☆26Jul 11, 2025Updated last year
- 32-bit Superscalar RISC-V CPU☆1,298Sep 18, 2021Updated 4 years ago
- IOMMU IP compliant with the RISC-V IOMMU Specification v1.0☆121Sep 24, 2025Updated 11 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆999Nov 15, 2024Updated last year
- RISC-V Processor Trace Specification☆221Updated this week
- pulp_soc is the core building component of PULP based SoCs☆85Jul 17, 2026Updated last month
- JTAG DPI module for SystemVerilog RTL simulations☆32Oct 30, 2015Updated 10 years ago
- RISC-V RV64GC emulator designed for RTL co-simulation☆244Nov 20, 2024Updated last year
- Random instruction generator for RISC-V processor verification☆1,351Apr 3, 2026Updated 4 months ago
- Capture retired instructions of a RISC-V Core and compress them to a sequence of packets.☆19Mar 13, 2024Updated 2 years ago