RISC-V Debug Support for our PULP RISC-V Cores
☆308Apr 1, 2026Updated last month
Alternatives and similar repositories for riscv-dbg
Users that are interested in riscv-dbg are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Generic Register Interface (contains various adapters)☆138Feb 24, 2026Updated 2 months ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,223Apr 17, 2026Updated 2 weeks ago
- The multi-core cluster of a PULP system.☆113Updated this week
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆224Jan 11, 2026Updated 3 months ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆160Oct 31, 2024Updated last year
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆208Apr 8, 2026Updated 3 weeks ago
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆269Nov 6, 2024Updated last year
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆86Feb 5, 2026Updated 2 months ago
- Fork of OpenOCD that has RISC-V support☆514Oct 9, 2025Updated 6 months ago
- Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)☆293Updated this week
- Common SystemVerilog components☆738Apr 27, 2026Updated last week
- Functional verification project for the CORE-V family of RISC-V cores.☆674Apr 16, 2026Updated 2 weeks ago
- Working Draft of the RISC-V Debug Specification Standard☆511Apr 8, 2026Updated 3 weeks ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,566Apr 22, 2026Updated last week
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- FuseSoC-based SoC for VeeR EH1 and EL2☆340Dec 11, 2024Updated last year
- Instruction Set Generator initially contributed by Futurewei☆308Oct 17, 2023Updated 2 years ago
- CORE-V Family of RISC-V Cores☆351Mar 31, 2026Updated last month
- RISC-V CPU Core☆426Jun 24, 2025Updated 10 months ago
- A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow …☆126Apr 1, 2026Updated last month
- This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…☆476Apr 16, 2026Updated 2 weeks ago
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,864Apr 14, 2026Updated 2 weeks ago
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆331Updated this week
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆594Apr 20, 2026Updated 2 weeks ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- RISC-V Processor Tracing tools and library☆16Mar 17, 2024Updated 2 years ago
- ☆264Dec 22, 2022Updated 3 years ago
- VeeR EL2 Core☆335Updated this week
- VeeR EH1 core☆938May 29, 2023Updated 2 years ago
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,913Updated this week
- RSD: RISC-V Out-of-Order Superscalar Processor☆1,170Feb 21, 2026Updated 2 months ago
- 32-bit Superscalar RISC-V CPU☆1,239Sep 18, 2021Updated 4 years ago
- ☆13May 5, 2023Updated 2 years ago
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆979Nov 15, 2024Updated last year
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- pulp_soc is the core building component of PULP based SoCs☆84Mar 10, 2025Updated last year
- JTAG DPI module for SystemVerilog RTL simulations☆32Oct 30, 2015Updated 10 years ago
- RISC-V Processor Trace Specification☆217Updated this week
- RISC-V RV64GC emulator designed for RTL co-simulation☆240Nov 20, 2024Updated last year
- Random instruction generator for RISC-V processor verification☆1,291Apr 3, 2026Updated last month
- ☆15Mar 9, 2026Updated last month
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆131Jul 11, 2025Updated 9 months ago