RTL blocks compatible with the Rocket Chip Generator
☆17Mar 30, 2025Updated last year
Alternatives and similar repositories for rocket-chip-blocks
Users that are interested in rocket-chip-blocks are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- PCB libraries and templates for rocket-chip based FPGA/ASIC designs☆20Updated this week
- Acceleration of TFHE-based Homomorphic NAND Gate on FPGA☆18Jul 7, 2021Updated 5 years ago
- Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boards☆20Aug 15, 2026Updated 2 months ago
- CoPHEE is a Co-processor for Partially Homomorphic Encrypted Encryption.☆36Feb 21, 2024Updated 2 years ago
- ☆92Oct 20, 2026Updated last week
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- LoongBleed (aka LoongLeak) is a hardware vulnerability similar to ZenBleed (CVE-2023-20593) affecting Loongson LA464/LA664 processors.☆17Aug 18, 2026Updated 2 months ago
- Run Unikraft ELF Loader app on Linux executables☆16Oct 19, 2023Updated 3 years ago
- RISC-V Processor Tracing tools and library☆16Mar 17, 2024Updated 2 years ago
- musl: A C standard library☆18Apr 20, 2026Updated 6 months ago
- Framework to perform DUT vs ISS (Whisper) lockstep architectural checks☆26Oct 15, 2025Updated last year
- Block-diagram style digital logic visualizer☆23Sep 16, 2015Updated 11 years ago
- Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)☆62Oct 1, 2023Updated 3 years ago
- UVM Testbench for a SRAM☆14Dec 18, 2020Updated 5 years ago
- Generate SystemVerilog/UVM block level testbench setup with python script☆11Oct 3, 2017Updated 9 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- ☆17May 22, 2023Updated 3 years ago
- Implementation of basic and advance level Data Structures with some important algorithms for Education purposes, using C and C++. Contrib…☆10Jun 21, 2022Updated 4 years ago
- A Rocket-based RISC-V superscalar in-order core☆42Oct 16, 2026Updated 2 weeks ago
- A project to perform the VLSI Physical Design Flow steps of partitioning, floorplan, placement and routing.☆13Jun 9, 2021Updated 5 years ago
- Flexible Open-source workBench fOr Side-channel analysis (FOBOS)☆18Nov 19, 2025Updated 11 months ago
- Library to compile Chisel circuits using LLVM/MLIR (CIRCT)☆70Mar 2, 2023Updated 3 years ago
- SiFive OpenEmbedded / Yocto BSP Layer☆58Updated this week
- chipyard in mill :P☆77Nov 20, 2023Updated 2 years ago
- CV32E40X Design-Verification environment☆19Jun 2, 2026Updated 4 months ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- This repository contains the specification source for the RISC-V IOPMP Specification. This document proposes a Physical Memory Protectio…☆42Updated this week
- Verilog implementation of 1024 bit Hybrid Montgomery Multiplication/Exponentiation☆14Nov 28, 2019Updated 6 years ago
- ☆19Jul 26, 2024Updated 2 years ago
- RISC-V Processor Trace Specification☆225Oct 23, 2026Updated last week
- Chisel/Firrtl execution engine☆157Aug 21, 2024Updated 2 years ago
- ☆40Mar 6, 2026Updated 7 months ago
- Exploring the Ed25519 (FPGA) design space.☆19Nov 23, 2017Updated 8 years ago
- RISC-V Nexus Trace TG documentation and reference code☆63Jul 21, 2026Updated 3 months ago
- ☆12Feb 22, 2024Updated 2 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆53Jul 14, 2020Updated 6 years ago
- Clock Fault Injector - Clock Glitching Attack with Chipwhisperer☆10Dec 26, 2024Updated last year
- Towards an Automated Triple Modular Redundancy (TMR) EDA flow for Yosys.☆12Aug 17, 2026Updated 2 months ago
- A tool to compile your RTL files into GDSII layouts.☆12Sep 9, 2025Updated last year
- Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.☆41Feb 6, 2024Updated 2 years ago
- Proof-of-concept implementation of a homomorphic Simon encryption using YASHE and FV leveled homomorphic cryptosystems☆20Aug 8, 2015Updated 11 years ago
- ☆29Mar 1, 2025Updated last year