Alternatives and similar repositories for rocket-chip-blocks

Users that are interested in rocket-chip-blocks are comparing it to the libraries listed below

• chipsalliance / rocket-chip-fpga-shells
  Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boards
  ☆19Updated 9 months ago
• OpenXiangShan / Utility
  ☆14Updated 2 weeks ago
• ucb-bar / shuttle
  A Rocket-based RISC-V superscalar in-order core
  ☆35Updated 4 months ago
• openhwgroup / cv32e40x-dv
  CV32E40X Design-Verification environment
  ☆13Updated last year
• OpenXiangShan / CoupledL2
  Open-source non-blocking L2 cache
  ☆48Updated this week
• jiegec / rocket-chip-vcu128
  Run Rocket Chip on VCU128
  ☆30Updated 9 months ago
• stnolting / neorv32-riscof
  ✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
  ☆34Updated this week
• freechipsproject / chisel-cheatsheet
  Chisel Cheatsheet
  ☆33Updated 2 years ago
• ucb-bar / testchipip
  ☆86Updated 3 months ago
• ucb-bar / cva6-wrapper
  Wrapper for ETH Ariane Core
  ☆21Updated 2 weeks ago
• OpenXiangShan / HuanCun
  Open-source high-performance non-blocking cache
  ☆88Updated last week
• jiegec / fpu-wrappers
  Wrappers for open source FPU hardware implementations.
  ☆33Updated last year
• pulp-platform / pulp-runtime
  Simple runtime for Pulp platforms
  ☆49Updated 3 weeks ago
• ducky64 / chisualizer
  Block-diagram style digital logic visualizer
  ☆23Updated 9 years ago
• circt / arc-tests
  A collection of tests and benchmarks for the Arc simulation backend of CIRCT
  ☆30Updated 3 weeks ago
• chipsalliance / rocket-chip-inclusive-cache
  An RTL generator for a last-level shared inclusive TileLink cache controller
  ☆22Updated 7 months ago
• aswaterman / trainwreck
  Original RISC-V 1.0 implementation. Not supported.
  ☆41Updated 6 years ago
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆65Updated 7 months ago
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆108Updated this week
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆63Updated last week
• ucb-bar / berkeley-testfloat-3
  TestFloat release 3
  ☆67Updated 6 months ago
• OpenXiangShan / YunSuan
  This repo includes XiangShan's function units
  ☆27Updated this week
• bespoke-silicon-group / bsg_replicant
  BSG Replicant: Cosimulation and Emulation Infrastructure for HammerBlade
  ☆35Updated 2 weeks ago
• pulp-platform / redmule
  ☆73Updated last week
• chipsalliance / playground
  chipyard in mill :P
  ☆78Updated last year
• IBM / chiffre
  A fault-injection framework using Chisel and FIRRTL
  ☆37Updated 4 months ago
• DFiantHDL / DFHDL
  DFiant HDL (DFHDL): A Dataflow Hardware Descripition Language
  ☆88Updated this week
• uec-hanken / tee-hardware
  TEE hardware - based on the chipyard repository - hardware to accelerate TEE
  ☆24Updated 2 years ago
• carlosedp / chiselv
  A RISC-V Core (RV32I) written in Chisel HDL
  ☆103Updated 3 weeks ago
• AlSaqr-platform / he-soc
  ☆32Updated last week