Alternatives and similar repositories for rocket-chip-blocks:

Users that are interested in rocket-chip-blocks are comparing it to the libraries listed below

• ucb-bar / cva6-wrapper
  Wrapper for ETH Ariane Core
  ☆20Updated last month
• chipsalliance / rocket-chip-fpga-shells
  Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boards
  ☆18Updated 5 months ago
• ucb-bar / shuttle
  A Rocket-based RISC-V superscalar in-order core
  ☆31Updated this week
• stnolting / neorv32-riscof
  ✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
  ☆33Updated this week
• openhwgroup / cv32e40x-dv
  CV32E40X Design-Verification environment
  ☆12Updated last year
• OpenXiangShan / YunSuan
  This repo includes XiangShan's function units
  ☆21Updated this week
• ucb-bar / nvdla-wrapper
  Wraps the NVDLA project for Chipyard integration
  ☆20Updated 3 weeks ago
• firesim / icenet
  Network components (NIC, Switch) for FireBox
  ☆17Updated 6 months ago
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆54Updated 3 months ago
• ucb-bar / barstools
  Useful utilities for BAR projects
  ☆31Updated last year
• jiegec / fpu-wrappers
  Wrappers for open source FPU hardware implementations.
  ☆31Updated last year
• IBM / chiffre
  A fault-injection framework using Chisel and FIRRTL
  ☆36Updated 2 years ago
• scarv / scarv-cpu
  SCARV: a side-channel hardened RISC-V platform
  ☆26Updated 2 years ago
• OpenXiangShan / CoupledL2
  Open-source non-blocking L2 cache
  ☆42Updated this week
• pulp-platform / culsans
  Tightly-coupled cache coherence unit for CVA6 using the ACE protocol
  ☆31Updated last year
• pulp-platform / axi_node
  AXI X-Bar
  ☆19Updated 5 years ago
• riscvarchive / riscv-zicond
  The ISA specification for the ZiCondOps extension.
  ☆19Updated last year
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆54Updated this week
• YosysHQ / yosys-tests
  Collection of test cases for Yosys
  ☆18Updated 3 years ago
• AlSaqr-platform / he-soc
  ☆31Updated this week
• comparch-security / FlexiCAS
  A Flexible Cache Architectural Simulator
  ☆14Updated 4 months ago
• openhwgroup / cv32e41p
  4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions
  ☆27Updated last year
• YosysHQ / abc
  ABC: System for Sequential Logic Synthesis and Formal Verification
  ☆27Updated 3 weeks ago
• ucb-bar / fixedpoint
  Chisel Fixed-Point Arithmetic Library
  ☆14Updated 3 months ago
• chipsalliance / tilelink
  ☆30Updated 4 months ago
• antmicro / verilator-old-archived
  ☆22Updated 2 years ago
• jiegec / rocket-chip-vcu128
  Run Rocket Chip on VCU128
  ☆30Updated 5 months ago
• pulp-platform / chimera
  ☆16Updated 2 weeks ago
• pulp-platform / pulp-runtime
  Simple runtime for Pulp platforms
  ☆45Updated last month
• zhemao / riscv-dma
  A DMA Controller for RISCV CPUs
  ☆14Updated 9 years ago