chipsalliance / rocket-chip-blocksLinks
RTL blocks compatible with the Rocket Chip Generator
☆16Updated 6 months ago
Alternatives and similar repositories for rocket-chip-blocks
Users that are interested in rocket-chip-blocks are comparing it to the libraries listed below
Sorting:
- Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boards☆19Updated 10 months ago
- CV32E40X Design-Verification environment☆13Updated last year
- A Rocket-based RISC-V superscalar in-order core☆35Updated 2 weeks ago
- ☆15Updated 2 weeks ago
- Original RISC-V 1.0 implementation. Not supported.☆42Updated 7 years ago
- An RTL generator for a last-level shared inclusive TileLink cache controller☆22Updated 9 months ago
- Open-source non-blocking L2 cache☆50Updated this week
- ✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.☆34Updated this week
- Wrapper for ETH Ariane Core☆21Updated last month
- Chisel Cheatsheet☆34Updated 2 years ago
- Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.☆39Updated last year
- ☆80Updated last week
- Run Rocket Chip on VCU128☆30Updated 2 weeks ago
- ☆86Updated 4 months ago
- ☆32Updated last week
- The specification for the FIRRTL language☆62Updated this week
- ☆32Updated this week
- The multi-core cluster of a PULP system.☆108Updated 3 weeks ago
- Simple runtime for Pulp platforms☆49Updated 3 weeks ago
- Open-source high-performance non-blocking cache☆90Updated last month
- Wrappers for open source FPU hardware implementations.☆34Updated last year
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆67Updated last month
- Infrastructure to drive Spike (RISC-V ISA Simulator) in cosim mode. Hammer provides a C++ and Python interface to interact with Spike.☆38Updated 2 months ago
- A fault-injection framework using Chisel and FIRRTL☆36Updated last month
- BSG Replicant: Cosimulation and Emulation Infrastructure for HammerBlade☆37Updated last month
- A collection of tests and benchmarks for the Arc simulation backend of CIRCT☆31Updated 2 months ago
- Network components (NIC, Switch) for FireBox☆19Updated 11 months ago
- chipyard in mill :P☆77Updated last year
- For contributions of Chisel IP to the chisel community.☆66Updated 11 months ago
- Block-diagram style digital logic visualizer☆23Updated 10 years ago