Alternatives and similar repositories for dromajo

Users that are interested in dromajo are comparing it to the libraries listed below

• riscv-ovpsim / imperas-riscv-tests
  ☆190Updated 2 years ago
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆204Updated last year
• bucaps / marss-riscv
  TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems
  ☆162Updated 3 years ago
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆302Updated 2 years ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆180Updated 7 months ago
• pulp-platform / snitch
  ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!
  ☆227Updated 2 years ago
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆276Updated 2 months ago
• SpinalHDL / NaxRiscv
  ☆301Updated last month
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆249Updated last year
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆166Updated 5 years ago
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆310Updated this week
• chipsalliance / VeeR-ISS
  ☆150Updated 2 years ago
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆288Updated 3 weeks ago
• pulp-platform / mempool
  A scalable 256/1024-RISC-V-core system with low-latency access into shared L1 memory.
  ☆312Updated last week
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆127Updated this week
• riscvarchive / riscv-CMOs
  ☆89Updated 3 months ago
• chipsalliance / Cores-VeeR-EH2
  ☆250Updated 2 years ago
• lowRISC / ariane
  Ariane is a 6-stage RISC-V CPU
  ☆151Updated 6 years ago
• IObundle / iob-soc
  RISC-V System on Chip Template
  ☆159Updated 4 months ago
• pulp-platform / cheshire
  A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
  ☆307Updated this week
• openhwgroup / programs
  Documentation for the OpenHW Group's set of CORE-V RISC-V cores
  ☆221Updated last month
• riscv-non-isa / riscv-trace-spec
  RISC-V Processor Trace Specification
  ☆198Updated 2 months ago
• tenstorrent / riscv-ocelot
  Ocelot: The Berkeley Out-of-Order Machine With V-EXT support
  ☆205Updated this week
• subbdue / systemverilog.io
  Code used in
  ☆199Updated 8 years ago
• openhwgroup / core-v-mcu
  This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
  ☆194Updated last week
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆78Updated last year
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆151Updated last year
• agra-uni-bremen / riscv-vp
  RISC-V Virtual Prototype
  ☆182Updated last year
• intel / systemc-compiler
  This tool translates synthesizable SystemC code to synthesizable SystemVerilog.
  ☆298Updated last month
• riscvarchive / riscv-code-size-reduction
  ☆147Updated last year