RISC-V RV64GC emulator designed for RTL co-simulation
☆241Nov 20, 2024Updated last year
Alternatives and similar repositories for dromajo
Users that are interested in dromajo are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- The RISC-V Architectural Certification Tests (ACTs) are a set of assembly language tests designed to certify that a design faithfully imp…☆711Updated this week
- Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model☆216Updated this week
- RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance☆381Oct 19, 2023Updated 2 years ago
- educational microarchitectures for risc-v isa☆746Sep 1, 2025Updated 9 months ago
- Random instruction generator for RISC-V processor verification☆1,303Apr 3, 2026Updated last month
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Instruction Set Generator initially contributed by Futurewei☆310Oct 17, 2023Updated 2 years ago
- A Linux-capable RISC-V multicore for and by the world☆805Apr 24, 2026Updated last month
- RISC-V Formal Verification Framework☆631Apr 6, 2022Updated 4 years ago
- RSD: RISC-V Out-of-Order Superscalar Processor☆1,179Feb 21, 2026Updated 3 months ago
- The OpenPiton Platform☆792Feb 25, 2026Updated 3 months ago
- Tile based architecture designed for computing efficiency, scalability and generality☆291Apr 30, 2026Updated last month
- ☆155Oct 6, 2023Updated 2 years ago
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆226Jan 11, 2026Updated 4 months ago
- high-performance RTL simulator☆193Jun 19, 2024Updated last year
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems☆165May 1, 2022Updated 4 years ago
- ☆201Dec 14, 2023Updated 2 years ago
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,947May 23, 2026Updated last week
- RISC-V SystemC-TLM simulator☆352Feb 20, 2026Updated 3 months ago
- Flexible Intermediate Representation for RTL☆750Aug 20, 2024Updated last year
- Testing processors with Random Instruction Generation☆59Jan 13, 2026Updated 4 months ago
- Modeling Architectural Platform☆224May 22, 2026Updated last week
- RISC-V Torture Test☆216Jul 11, 2024Updated last year
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆270Nov 6, 2024Updated last year
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- Sail RISC-V model☆708Updated this week
- Digital Design with Chisel☆914Apr 30, 2026Updated last month
- The multi-core cluster of a PULP system.☆114May 25, 2026Updated last week
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆321Mar 6, 2026Updated 2 months ago
- Functional verification project for the CORE-V family of RISC-V cores.☆682Apr 16, 2026Updated last month
- Common SystemVerilog components☆754Updated this week
- VeeR EH1 core☆945May 29, 2023Updated 3 years ago
- ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!☆229Nov 22, 2023Updated 2 years ago
- ☆90May 23, 2026Updated last week
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- ☆30Mar 31, 2025Updated last year
- RISC-V Verification Interface☆152Mar 27, 2026Updated 2 months ago
- Minimal RISC-V Chisel design strictly reflecting the ISA document for verification.☆20Apr 14, 2026Updated last month
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆606Updated this week
- ☆1,197May 1, 2026Updated last month
- RISC-V Processor Trace Specification☆217May 25, 2026Updated last week
- A wrapper for the SPEC CPU2006 benchmark suite.☆93May 6, 2021Updated 5 years ago