chipsalliance / dromajoLinks
RISC-V RV64GC emulator designed for RTL co-simulation
☆230Updated 9 months ago
Alternatives and similar repositories for dromajo
Users that are interested in dromajo are comparing it to the libraries listed below
Sorting:
- RISC-V Torture Test☆197Updated last year
- Tile based architecture designed for computing efficiency, scalability and generality☆263Updated 2 months ago
- TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems☆155Updated 3 years ago
- Instruction Set Generator initially contributed by Futurewei☆292Updated last year
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆179Updated 3 months ago
- ☆182Updated last year
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆244Updated 9 months ago
- ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!☆226Updated last year
- RiscyOO: RISC-V Out-of-Order Processor☆160Updated 5 years ago
- RISC-V Debug Support for our PULP RISC-V Cores☆266Updated 4 months ago
- ☆293Updated last week
- VeeR EL2 Core☆294Updated last week
- ☆242Updated 2 years ago
- Ocelot: The Berkeley Out-of-Order Machine With V-EXT support☆174Updated this week
- ☆143Updated last year
- A 256-RISC-V-core system with low-latency access into shared L1 memory.☆302Updated last week
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆275Updated this week
- RISC-V Processor Trace Specification☆192Updated 2 weeks ago
- ☆149Updated last year
- Ariane is a 6-stage RISC-V CPU☆142Updated 5 years ago
- Verilog Configurable Cache☆181Updated 8 months ago
- RISC-V Virtual Prototype☆174Updated 8 months ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆114Updated this week
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆218Updated 3 months ago
- RISC-V CPU Core☆369Updated last month
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆73Updated last year
- ☆336Updated 11 months ago
- ☆89Updated 3 years ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆150Updated 9 months ago
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆186Updated last month