chipsalliance / dromajo
RISC-V RV64GC emulator designed for RTL co-simulation
☆221Updated 3 months ago
Alternatives and similar repositories for dromajo:
Users that are interested in dromajo are comparing it to the libraries listed below
- Instruction Set Generator initially contributed by Futurewei☆272Updated last year
- ☆168Updated last year
- RISC-V Torture Test☆179Updated 7 months ago
- Tile based architecture designed for computing efficiency, scalability and generality☆244Updated this week
- ☆275Updated last week
- RiscyOO: RISC-V Out-of-Order Processor☆154Updated 4 years ago
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆226Updated 3 months ago
- RISC-V Debug Support for our PULP RISC-V Cores☆243Updated 3 months ago
- RISC-V CPU Core☆311Updated 8 months ago
- VeeR EL2 Core☆263Updated this week
- TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems☆147Updated 2 years ago
- ☆225Updated 2 years ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆166Updated 6 months ago
- ☆303Updated 5 months ago
- ☆129Updated last year
- Common RTL blocks used in SiFive's projects☆182Updated 2 years ago
- Verilog Configurable Cache☆170Updated 2 months ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆455Updated last week
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆205Updated last week
- Ariane is a 6-stage RISC-V CPU☆130Updated 5 years ago
- FuseSoC-based SoC for VeeR EH1 and EL2☆306Updated 2 months ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆142Updated 3 months ago
- SystemC/TLM-2.0 Co-simulation framework☆232Updated 3 months ago
- ☆84Updated 2 years ago
- A Fast, Low-Overhead On-chip Network☆169Updated last week
- Ocelot: The Berkeley Out-of-Order Machine With V-EXT support☆156Updated last month
- Working draft of the proposed RISC-V Bitmanipulation extension☆208Updated 11 months ago
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆398Updated this week
- A Chisel RTL generator for network-on-chip interconnects☆183Updated 3 months ago
- ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!☆219Updated last year