chipsalliance / dromajo
RISC-V RV64GC emulator designed for RTL co-simulation
☆222Updated 3 months ago
Alternatives and similar repositories for dromajo:
Users that are interested in dromajo are comparing it to the libraries listed below
- ☆168Updated last year
- Instruction Set Generator initially contributed by Futurewei☆273Updated last year
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆225Updated 4 months ago
- RISC-V Torture Test☆183Updated 8 months ago
- RISC-V Debug Support for our PULP RISC-V Cores☆246Updated 4 months ago
- Tile based architecture designed for computing efficiency, scalability and generality☆246Updated last week
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆206Updated this week
- ☆275Updated this week
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆169Updated 7 months ago
- Verilog Configurable Cache☆172Updated 3 months ago
- TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems☆150Updated 2 years ago
- VeeR EL2 Core☆266Updated this week
- ☆229Updated 2 years ago
- RiscyOO: RISC-V Out-of-Order Processor☆154Updated 4 years ago
- RISC-V CPU Core☆317Updated 9 months ago
- ☆310Updated 6 months ago
- RISC-V Processor Trace Specification☆172Updated last week
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆459Updated last month
- ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!☆219Updated last year
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆143Updated 4 months ago
- ☆129Updated last year
- A Fast, Low-Overhead On-chip Network☆181Updated last week
- ☆151Updated last year
- RISC-V System on Chip Template☆156Updated this week
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆210Updated 4 years ago
- Working draft of the proposed RISC-V Bitmanipulation extension☆209Updated 11 months ago
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆230Updated last week
- FuseSoC-based SoC for VeeR EH1 and EL2☆308Updated 3 months ago
- Ariane is a 6-stage RISC-V CPU☆132Updated 5 years ago
- CORE-V Family of RISC-V Cores☆240Updated last month