chipsalliance / dromajoLinks
RISC-V RV64GC emulator designed for RTL co-simulation
☆235Updated 11 months ago
Alternatives and similar repositories for dromajo
Users that are interested in dromajo are comparing it to the libraries listed below
Sorting:
- RISC-V Torture Test☆202Updated last year
- ☆189Updated last year
- Tile based architecture designed for computing efficiency, scalability and generality☆273Updated last month
- TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems☆161Updated 3 years ago
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆245Updated last year
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆177Updated 6 months ago
- Instruction Set Generator initially contributed by Futurewei☆298Updated 2 years ago
- ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!☆226Updated last year
- RiscyOO: RISC-V Out-of-Order Processor☆164Updated 5 years ago
- ☆301Updated last week
- ☆247Updated 2 years ago
- ☆150Updated 2 years ago
- RISC-V Debug Support for our PULP RISC-V Cores☆278Updated 3 weeks ago
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆295Updated last week
- VeeR EL2 Core☆302Updated last week
- A scalable 256/1024-RISC-V-core system with low-latency access into shared L1 memory.☆309Updated last week
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆219Updated 5 months ago
- RISC-V Processor Trace Specification☆195Updated last month
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆186Updated last month
- Ariane is a 6-stage RISC-V CPU☆151Updated 5 years ago
- Ocelot: The Berkeley Out-of-Order Machine With V-EXT support☆192Updated this week
- ☆89Updated 2 months ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆123Updated last week
- Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model☆190Updated 2 weeks ago
- RISC-V System on Chip Template☆159Updated 2 months ago
- RISC-V Virtual Prototype☆179Updated 10 months ago
- RISC-V CPU Core☆392Updated 4 months ago
- RISC-V soft-core microcontroller for FPGA implementation☆186Updated 3 weeks ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆149Updated 2 weeks ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆76Updated last year