RISC-V Configuration Validator
☆82Mar 28, 2025Updated 11 months ago
Alternatives and similar repositories for riscv-config
Users that are interested in riscv-config are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆148Feb 29, 2024Updated 2 years ago
- ☆41Nov 4, 2024Updated last year
- ☆103Aug 29, 2025Updated 6 months ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions☆26Aug 16, 2023Updated 2 years ago
- ☆665Updated this week
- RISC-V Architecture Profiles☆177Mar 13, 2026Updated last week
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆156Oct 31, 2024Updated last year
- AIA IP compliant with the RISC-V AIA spec☆46Jan 27, 2025Updated last year
- Sail RISC-V model☆679Mar 17, 2026Updated last week
- ☆35Nov 4, 2024Updated last year
- Yocto project for Xuantie RISC-V CPU☆41Mar 18, 2026Updated last week
- Working Draft of the RISC-V Debug Specification Standard☆507Mar 14, 2026Updated last week
- RISC-V Packed SIMD Extension☆161Updated this week
- ☆12Feb 15, 2024Updated 2 years ago
- Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)☆290Updated this week
- RISC-V Configuration Structure☆41Oct 30, 2024Updated last year
- RISC-V Proxy Kernel☆689Oct 2, 2025Updated 5 months ago
- Dual-issue RV64IM processor for fun & learning☆64Jul 4, 2023Updated 2 years ago
- The ISA specification for the ZiCondOps extension.☆19Mar 21, 2024Updated 2 years ago
- KVM RISC-V HowTOs☆47Jun 9, 2022Updated 3 years ago
- Host software for running SSITH processors on AWS F1 FPGAs☆20Jul 20, 2021Updated 4 years ago
- RISC-V Processor Trace Specification☆209Mar 18, 2026Updated last week
- This repository contains the specification source for the RISC-V IOPMP Specification. This document proposes a Physical Memory Protectio…☆38Mar 7, 2026Updated 2 weeks ago
- Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.☆39Feb 6, 2024Updated 2 years ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆80May 22, 2024Updated last year
- ☆34Updated this week
- RISC-V IOMMU Specification☆152Mar 14, 2026Updated last week
- My second attempt at a RISC-V CPU with learnings form my previous attempt.☆10Apr 29, 2024Updated last year
- RISC-V Vector (RVV) Automatic Tests Generator with full instructions coverage, including self-checking test and signature test (RISC-V Co…☆16Apr 3, 2024Updated last year
- RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance☆377Oct 19, 2023Updated 2 years ago
- Description of a RISC-V architecture based on MIPS 3000☆13Apr 24, 2023Updated 2 years ago
- Main Repo for the OpenHW Group Software Task Group☆17Mar 11, 2025Updated last year
- PLIC Specification☆152Updated this week
- RISC-V BSV Specification☆23Jan 18, 2020Updated 6 years ago
- ☆18Jul 26, 2024Updated last year
- Documenting the expected behaviour and supported command-line switches for GNU and LLVM based RISC-V toolchains☆151Updated this week
- RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)☆335Jan 23, 2022Updated 4 years ago
- pulp_soc is the core building component of PULP based SoCs☆83Mar 10, 2025Updated last year
- RISC-V processor☆32May 26, 2022Updated 3 years ago