A eDSL framework based on Scala and MLIR, focusing on the Hardware design.
☆71May 23, 2026Updated this week
Alternatives and similar repositories for zaozi
Users that are interested in zaozi are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- The Scala parser to parse riscv/riscv-opcodes generate☆24Jan 21, 2026Updated 4 months ago
- Nix template for the chisel-based industrial designing flows.☆57Apr 23, 2025Updated last year
- This is an IDE for YSYX_NPC debuging☆12Dec 10, 2024Updated last year
- Basic chisel difftest environment for RTL design (WIP☆21Mar 8, 2025Updated last year
- A riscv emulator.☆19Feb 5, 2024Updated 2 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- ☆29Jun 19, 2025Updated 11 months ago
- 本项目已被合并至官方Chiplab中☆14Jan 13, 2025Updated last year
- A collection of tests and benchmarks for the Arc simulation backend of CIRCT☆38Jan 26, 2026Updated 4 months ago
- high-performance RTL simulator☆193Jun 19, 2024Updated last year
- MIPS R10000 architecture simulator with C++☆10Jun 8, 2023Updated 2 years ago
- ☆17Updated this week
- Unofficial guide for ysyx students applying to ShanghaiTech University☆24Mar 31, 2026Updated last month
- ☆53Jan 16, 2025Updated last year
- ☆44Dec 5, 2025Updated 5 months ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- This is a project created and completed by team BOOM(Beihang OO masters).This is a superscalar processor with a 13-stage out-of-order dua…☆18Sep 29, 2024Updated last year
- A dynamic verification library for Chisel.☆162Nov 9, 2024Updated last year
- Second Prize in NSCSCC 2024. An out-of-order CPU designed by NoAXI team from HDU. 2024年全国大学生计算机系统能力大赛CPU设计赛（龙芯杯）团队赛二等奖作品☆24Sep 14, 2024Updated last year
- ☆71May 11, 2026Updated 2 weeks ago
- 给NEMU移植Linux Kernel!☆23Jun 1, 2025Updated 11 months ago
- ☆317May 13, 2026Updated last week
- Vivado in GitLab-Runner for GitLab CI/CD☆10Oct 27, 2022Updated 3 years ago
- ☆38Jul 22, 2025Updated 10 months ago
- ☆67Aug 5, 2024Updated last year
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- SimCommand is a library for writing high-performance RTL testbenches with simulation threads in Scala using chiseltest.☆15Aug 30, 2023Updated 2 years ago
- Simple RISC-V 3-stage Pipeline in Chisel☆610Aug 9, 2024Updated last year
- Mirror of https://gitee.com/loongson-edu/open-la500.git☆26Jan 2, 2025Updated last year
- Modern co-simulation framework for RISC-V CPUs☆175Updated this week
- ☆71Feb 2, 2026Updated 3 months ago
- Example of Chisel3 Diplomacy☆11Feb 23, 2022Updated 4 years ago
- ☆11Dec 23, 2025Updated 5 months ago
- The Next-gen Language & Compiler Powering Efficient Hardware Design☆38Jan 16, 2025Updated last year
- ☆14Aug 31, 2025Updated 8 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- A core language for rule-based hardware design 🦑☆173Dec 10, 2025Updated 5 months ago
- ☆25Dec 4, 2025Updated 5 months ago
- Examples for creating AXI-interfaced peripherals in Chisel☆75Nov 15, 2015Updated 10 years ago
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆39May 18, 2026Updated last week
- Example code for an MMIO plugin for Spike, the RISC-V ISA simulator.☆12Aug 29, 2019Updated 6 years ago
- ☆82Oct 29, 2024Updated last year
- Chisel3 AXI4-{Lite, Full, Stream} Definitions☆15Dec 31, 2018Updated 7 years ago