A eDSL framework based on Scala and MLIR, focusing on the Hardware design.
☆76Aug 12, 2026Updated this week
Alternatives and similar repositories for zaozi
Users that are interested in zaozi are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- The Scala parser to parse riscv/riscv-opcodes generate☆26Jan 21, 2026Updated 6 months ago
- Nix template for the chisel-based industrial designing flows.☆58Jul 21, 2026Updated 3 weeks ago
- Basic chisel difftest environment for RTL design (WIP☆21Mar 8, 2025Updated last year
- ☆17Updated this week
- ☆16Aug 26, 2025Updated 11 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆79Updated this week
- This is an IDE for YSYX_NPC debuging☆12Dec 10, 2024Updated last year
- The 'missing header' for Chisel☆24Feb 5, 2026Updated 6 months ago
- high-performance RTL simulator☆195Aug 4, 2026Updated last week
- A collection of tests and benchmarks for the Arc simulation backend of CIRCT☆39Jan 26, 2026Updated 6 months ago
- A riscv emulator.☆19Feb 5, 2024Updated 2 years ago
- ☆45Dec 5, 2025Updated 8 months ago
- ☆30Jun 19, 2025Updated last year
- 本项目已被合并至官方Chiplab中☆14Jan 13, 2025Updated last year
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- ☆52Jan 16, 2025Updated last year
- The specification for the FIRRTL language☆66Updated this week
- ☆320Jul 22, 2026Updated 3 weeks ago
- ☆15Dec 9, 2025Updated 8 months ago
- 给NEMU移植Linux Kernel!☆23Jun 1, 2025Updated last year
- MIPS R10000 architecture simulator with C++☆11Jun 8, 2023Updated 3 years ago
- A dynamic verification library for Chisel.☆163Nov 9, 2024Updated last year
- Simple RISC-V 3-stage Pipeline in Chisel☆619Aug 9, 2024Updated 2 years ago
- A Heterogeneous GPU Platform for AI and Neural Graphics☆67Updated this week
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Mirror of https://gitee.com/loongson-edu/open-la500.git☆29Jan 2, 2025Updated last year
- Unofficial guide for ysyx students applying to ShanghaiTech University☆24Mar 31, 2026Updated 4 months ago
- Modern co-simulation framework for RISC-V CPUs☆182Updated this week
- This is a project created and completed by team BOOM(Beihang OO masters).This is a superscalar processor with a 13-stage out-of-order dua…☆18Sep 29, 2024Updated last year
- ☆67Aug 5, 2024Updated 2 years ago
- ☆15Jul 28, 2026Updated 2 weeks ago
- Second Prize in NSCSCC 2024. An out-of-order CPU designed by NoAXI team from HDU. 2024年全国大学生计算机系统能力大赛CPU设计赛（龙芯杯）团队赛二等奖作品☆26Sep 14, 2024Updated last year
- Sail RISC-V model☆749Updated this week
- Examples for creating AXI-interfaced peripherals in Chisel☆76Nov 15, 2015Updated 10 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- nscscc2024，HPU河南理工大学参赛作品，两仪处理器☆13Aug 24, 2024Updated last year
- 🌊 Tool for RTL waveform (VCD/FST) inspection via CLI☆50Updated this week
- Vivado in GitLab-Runner for GitLab CI/CD☆10Oct 27, 2022Updated 3 years ago
- ☆28Dec 4, 2025Updated 8 months ago
- ☆13Feb 13, 2021Updated 5 years ago
- CIRCT and Yosys interoperability, demonstrated with CHISEL☆17Feb 3, 2026Updated 6 months ago
- A core language for rule-based hardware design 🦑☆182Dec 10, 2025Updated 8 months ago